Philips Semiconductors Preliminary data
P87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2002 Mar 12
52
COMPARATOR ELECTRICAL CHARACTERISTICS
V
DD
= 3.0 V to 6.0 V unless otherwise specified; T
amb
= –40 °C to +125 °C, unless otherwise specified
LIMITS
MIN TYP MAX
V
IO
Offset voltage comparator inputs
1
±10 mV
V
CR
Common mode range comparator inputs 0 V
DD
–0.3 V
CMRR Common mode rejection ratio
1
–50 dB
Response time 250 500 ns
Comparator enable to output valid 10 µs
I
IL
Input leakage current, comparator 0 < V
IN
< V
DD
±10 µA
NOTE:
1. This parameter is guaranteed by characterization, but not tested in production.
A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Vdd = 2.7 V to 6.0 V unless otherwise specified; Tamb = –40 °C to +125 °C, unless otherwise specified.
LIMITS
MIN MAX
AV
IN
Analog input voltage V
SS
- 0.2 V
DD
+ 0.2 V
R
REF
Resistance between V
DD
and V
SS
A/D enabled tbd tbd kΩ
C
IA
Analog input capacitance 15 pF
DL
e
Differential non-linearity
1,2,3
±1 LSB
IL
e
Integral non-linearity
1,4
±1 LSB
OS
e
Offset error
1,5
±2 LSB
G
e
Gain error
1,6
±1 %
A
e
Absolute voltage error
1,7
±1 LSB
M
CTC
Channel-to-channel matching ±1 LSB
C
t
Crosstalk between inputs of port
8
0 - 100kHz -60 dB
- Input slew rate 100 V/ms
- Input source impedance 10 kΩ
NOTES:
1. Conditions: V
SS
= 0V; V
DD
= 5.12V.
2. The A/D is monotonic, there are no missing codes
3. The differential non-linearity (DL
e
) is the difference between the actual step width and the ideal step width. See Figure 41.
4. The integral non-linearity (IL
e
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 41.
5. The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 41.
6. The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 41.
7. The absolute voltage error (A
e
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to A/D pins.
9. Changing the input voltage faster than this may cause erroneous readings.
10.A source impedance higher than this driving an A/D input may result in loss of precision and erroneous readings.
