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transitions for the demodulator bit timing recovery, and
makes sure that the transmitted spectrum does not have
discrete lines even if the transmitted data is cyclic. It
does so without adding additional bits, i.e. without
changing the data rate. Spectral Shaping uses a
selfsynchronizing feedback shift register.
The encoder is programmed using the register
ENCODING, details and recommendations on usage are
given in the AX5051 Programming Manual.
Framing and FIFO
Most radio systems today group data into packets. The
framing unit is responsible for converting these packets into
a bitstream suitable for the modulator, and to extract
packets from the continuous bitstream arriving from the
demodulator.
The Framing unit supports four different modes:
HDLC
Raw
Raw with Preamble Match
802.15.4 Compliant
The microcontroller communicates with the framing
unit through a 4 level × 10 bit FIFO. The FIFO decouples
microcontroller timing from the radio (modulator and
demodulator) timing. The bottom 8 bits of the FIFO contain
transmit or receive data. The top 2 bit are used to convey
meta information in HDLC and 802.15.4 modes. They are
unused in Raw and Raw with Preamble Match modes. The
meta information consists of packet begin / end information
and the result of CRC checks.
The AX5051 contains one FIFO. Its direction is switched
depending on whether transmit or receive mode is selected.
The FIFO can be operated in polled or interrupt driven
modes. In polled mode, the microcontroller must
periodically read the FIFO status register or the FIFO count
register to determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT
FULL and programmable level interrupts are provided. The
AX5051 signals interrupts by asserting (driving high) its
IRQ line. The interrupt line is level triggered, active high.
Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun,
and the top two bits of the top FIFO word) are also provided
during each SPI access on MISO while the microcontroller
shifts out the register address on MOSI. See the SPI interface
section for details. This feature significantly reduces the
number of SPI accesses necessary during transmit and
receive.
HDLC Mode
NOTE: HDLC mode follows HighLevel Data Link
Control (HDLC, ISO 13239) protocol.
HDLC Mode is the main framing mode of the AX5051. In
this mode, the AX5051 performs automatic packet
delimiting, and optional packet correctness check by
inserting and checking a cyclic redundancy check (CRC)
field.
The packet structure is given in the following table.
Table 14.
Flag Address Control Information FCS (Optional Flag)
8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit
HDLC packets are delimited with flag sequences of
content 0x7E.
In AX5051 the meaning of address and control is user
defined. The Frame Check Sequence (FCS) can be
programmed to be CRCCCITT, CRC16 or CRC32.
The receiver checks the CRC, the result can be retrieved
from the FIFO, the CRC is appended to the received data.
For details on implementing a HDLC communication see
the AX5051 Programming Manual.
Raw Mode
In Raw mode, the AX5051 does not perform any packet
delimiting or byte synchronization. It simply serializes
transmit bytes and deserializes the received bitstream and
groups it into bytes.
This mode is ideal for implementing legacy protocols in
software.
Raw Mode with Preamble Match
Raw mode with preamble match is similar to raw mode.
In this mode, however, the receiver does not receive
anything until it detects a user programmable bit pattern
(called the preamble) in the receive bitstream. When it
detects the preamble, it aligns the deserialization to it.
The preamble can be between 4 and 32 bits long.
802.15.4 (ZigBee) DSSS
802.15.4 uses binary phase shift keying (PSK) with
300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on
the radio. The usable bit rate is only a 15
th
of the radio bit
rate, however. A spreading function in the transmitter
expands the user bit rate by a factor of 15, to make the
transmission more robust. The despreader function of the
receiver undoes that.
In 802.15.4 mode, the AX5051 framing unit performs the
spreading and despreading function according to the
802.15.4 specification. In receive mode, the framing unit
will also automatically search for the 802.15.4 preamble,
meaning that no interrupts will have to be serviced by the
microcontroller until a packet start is detected.
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The 802.15.4 is a universal DSSS mode, which can be
used with any modulation or data rate as long as it does not
violate the maximum data rate of the modulation being used.
Therefore the maximum DSSS data rate is 16 kbps for FSK
and 40 kbps for ASK and PSK.
RX AGC and RSSI
AX5051 features two receiver signal strength indicators
(RSSI):
1. RSSI before the digital IF channel filter.
The gain of the receiver is adjusted in order to
keep the analog IF filter output level inside the
working range of the ADC and demodulator. The
register AGCCOUNTER contains the current
value of the AGC and can be used as an RSSI. The
step size of this RSSI is 0.625 dB. The value can
be used as soon as the RF frequency generation
subsystem has been programmed.
2. RSSI behind the digital IF channel filter.
The demodulator also provides amplitude
information in the TRK_AMPLITUDE register.
By combining both the AGCCOUNTER and the
TRK_AMPLITUDE registers, a high resolution
(better than 0.1 dB) RSSI value can be computed
at the expense of a few arithmetic operations on
the microcontroller. Formulas for this
computation can be found in the AX5051
Programming Manual.
Modulator
Depending on the transmitter settings the modulator
generates various inputs for the PA (see Table 15):
Table 15.
Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate
ASK PA off PA on BW = BITRATE 600 kBit/s
FSK/MSK
Df = f
deviation
Df = +f
deviation
BW = (1 + h) BITRATE 350 kBit/s
PSK
DF = 0° DF = 180°
BW = BITRATE 600 kBit/s
Table 16.
h Modulation index. It is the ratio of the deviation compared to the bitrate.
AX5051 can demodulate signals with h < 32.
f
deviation
0.5hBITRATE
ASK Amplitude shift keying
FSK Frequency shift keying
MSK Minimum shift keying.
MSK is a special case of FSK, where h = 0.5, and therefore f
deviation
= 0.25BITRATE; the advantage of MSK over FSK is
that it can be demodulated more robustly.
PSK Phase shift keying
OQPSK Offset quadrature shift keying.
The AX5051 supports OQPSK. However, unless compatibility to an existing system is required, MSK should be preferred.
All modulation schemes are binary.
Automatic Frequency Control (AFC)
The AX5051 has a frequency tracking register
TRKFREQ to synchronize the receiver frequency to a
carrier signal. For AFC adjustment, the frequency offset can
be computed with the following formula:
Df +
TRKFREQ
2
16
BITRATE FSKMUL
FSKMUL is the FSK oversampling factor, it depends on
the FSK bitrate and deviation used. To determine it for a
specific case, see the AX5051 Programming Manual. For
modulations other than FSK, FSKMUL = 1.
PWRMODE Register
The PWRMODE register controls, which parts of the chip
are operating.
Table 17. PWRMODE REGISTER
PWRMODE Register Name Description Typical Idd
0000 POWERDOWN All digital and analog functions, except the register file, are disabled. The
core supply voltage is reduced to conserve leakage power. SPI registers
are still accessible, but at a slower speed.
0.5 mA
0100 VREGON All digital and analog functions, except the register file, are disabled. The
core voltage, however is at its nominal value for operation, and all SPI
registers are accessible at the maximum speed.
200 mA
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Table 17. PWRMODE REGISTER
PWRMODE Register Typical IddDescriptionName
0101 STANDBY The crystal oscillator is powered on; receiver and transmitter are off.
650 mA
1000 SYNTHRX The synthesizer is running on the receive frequency. Transmitter and
receiver are still off. This mode is used to let the synthesizer settle on the
correct frequency for receive.
11 mA
1001 FULLRX Synthesizer and receiver are running. 17 19 mA
1100 SYNTHTX The synthesizer is running on the transmit frequency. Transmitter and
receiver are still off. This mode is used to let the synthesizer settle on the
correct frequency for transmit.
10 mA
1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode
before the synthesizer has completely settled on the transmit frequency (in
SYNTHTX mode), otherwise spurious spectral transmissions will occur.
11 45 mA
Table 18. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION
Step PWRMODE Remarks
1 POWERDOWN
2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.
3 SYNTHTX
The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics
4 FULLTX Data transmission
5 SYNTHTX This step must be programmed after FULLTX mode, or the device will not enter
POWERDOWN or STANDBY mode.
6 POWERDOWN
Table 19. A TYPICAL PWRMODE SEQUENCE FOR A RECEIVE SESSION
Step PWRMODE [3:0] Remarks
1 POWERDOWN
2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.
3 SYNTHRX
The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics
4 FULLRX Data reception
5 POWERDOWN
Serial Peripheral Interface
The AX5051 can be programmed via a four wire serial
interface according SPI using the pins CLK, MOSI, MISO
and SEL. Registers for setting up the AX5051 are
programmed via the serial peripheral interface in all device
modes.
When the interface signal SEL is pulled low, a 16bit
configuration data stream is expected on the input signal pin
MOSI, which is interpreted as D0...D7, A0...A6, R_N/W.
Data read from the interface appears on MISO.
Figure 3 shows a write/read access to the interface. The
data stream is built of an address byte including read/write
information and a data byte. Depending on the R_N/W bit
and address bits A[6..0], data D[7..0] can be written via
MOSI or read at the pin MISO.
R_N/W = 0 means read mode, R_N/W = 1 means write
mode.
The read sequence starts with 7 bits of status information
S[6..0] followed by 8 data bits.
The status bits contain the following information:
Table 20.
S6 S5 S4 S3 S2 S1 S0
PLL LOCK FIFO OVER FIFO UNDER FIFO FULL FIFO EMPTY FIFOSTAT(1) FIFOSTAT(0)

AX5051-1-TW30

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RF Transceiver RADIO TRANSCEIVER
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