CAT28F512
4
Doc. No. MD-1084, Rev. K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Unit Test Conditions
I
LI
Input Leakage Current ±1 µAV
IN
= V
CC
or V
SS
V
CC
= 5.5V, OE = V
IH
I
LO
Output Leakage Current ±1 µAV
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V, OE = V
IH
I
SB1
V
CC
Standby Current CMOS 100 µA CE = V
CC
±0.5V,
V
CC
= 5.5V
I
SB2
V
CC
Standby Current TTL 1 mA CE = V
IH
, V
CC
= 5.5V
I
CC1
V
CC
Active Read Current 30 mA V
CC
= 5.5V, CE = V
IL
,
I
OUT
= 0mA, f = 6 MHz
I
CC2
(1)
V
CC
Programming Current 15 mA V
CC
= 5.5V,
Programming in Progress
I
CC3
(1)
V
CC
Erase Current 15 mA V
CC
= 5.5V,
Erasure in Progress
I
CC4
(1)
V
CC
Prog./Erase Verify Current 15 mA V
CC
= 5.5V, Program or
Erase Verify in Progress
I
PPS
V
PP
Standby Current ±10 µAV
PP
= V
PPL
I
PP1
V
PP
Read Current 200 µAV
PP
= V
PPH
I
PP2
(1)
V
PP
Programming Current 30 mA V
PP
= V
PPH
,
Programming in Progress
I
PP3
(1)
V
PP
Erase Current 30 mA V
PP
= V
PPH
,
Erasure in Progress
I
PP4
(1)
V
PP
Prog./Erase Verify Current 5 mA V
PP
= V
PPH
, Program or
Erase Verify in Progress
V
IL
Input Low Level TTL –0.5 0.8 V
V
ILC
Input Low Level CMOS –0.5 0.8 V
V
OL
Output Low Level 0.45 V I
OL
= 5.8mA, V
CC
= 4.5V
V
IH
Input High Level TTL 2 V
CC
+0.5 V
V
IHC
Input High Level CMOS V
CC
*0.7 V
CC
+0.5 V
V
OH1
Output High Level TTL 2.4 V I
OH
= –2.5mA, V
CC
= 4.5V
V
OH2
Output High Level CMOS V
CC
–0.4 V I
OH
= –400µA, V
CC
= 4.5V
V
ID
A
9
Signature Voltage 11.4 13 V A
9
= V
ID
I
ID
(1)
A
9
Signature Current 200 µAA
9
= V
ID
V
LO
V
CC
Erase/Prog. Lockout Voltage 2.5 V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT28F512
5
Doc. No. MD-1084, Rev. K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
SUPPLY CHARACTERISTICS
Limits
Symbol Parameter Min Max. Unit
V
CC
V
CC
Supply Voltage 4.5 5.5 V
V
PPL
V
PP
During Read Operations 0 6.5 V
V
PPH
V
PP
During Read/Erase/Program 11.4 12.6 V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
C
L
= 100 pF
OUT
C
L
INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V ±10%, unless otherwise specified.
JEDEC Standard 28F512-90 28F512-12 28F512-15
Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
AVAV
t
RC
Read Cycle Time 90 120 150 ns
t
ELQV
t
CE
CE Access Time 90 120 150 ns
t
AVQV
t
ACC
Address Access Time 90 120 150 ns
t
GLQV
t
OE
OE Access Time 35 50 55 ns
t
AXQX
t
OH
Output Hold from Address OE/CE Change 0 0 0 ns
t
GLQX
t
OLZ
(1)(6)
OE to Output in Low-Z 0 0 0 ns
t
ELQX
t
LZ
(1)(6)
CE to Output in Low-Z 0 0 0 ns
t
GHQZ
t
DF
(1)(2)
OE High to Output High-Z 20 30 35 ns
t
EHQZ
t
DF
(1)(2)
CE High to Output High-Z 30 40 45 ns
t
WHGL
(1)
- Write Recovery Time Before Read 6 6 6 µs
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
Figure 1. A.C. Testing Input/Output Waveform
(3)(4)(5)
Figure 2. A.C. Testing Load Circuit (example)
CAT28F512
6
Doc. No. MD-1084, Rev. K
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
A.C. CHARACTERISTICS, Program/Erase Operation
V
CC
= +5V ±10%, unless otherwise specified.
JEDEC
Standard
28F512-90 28F512-12 28F512-15
Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
AVAV
t
WC
Write Cycle Time 90 120 150 ns
t
AVWL
t
AS
Address Setup Time 0 0 0 ns
t
WLAX
t
AH
Address Hold Time 40 40 40 ns
t
DVWH
t
DS
Data Setup Time 40 40 40 ns
t
WHDX
t
DH
Data Hold Time 10 10 10 ns
t
ELWL
t
CS
CE Setup Time 0 0 0 ns
t
WHEH
t
CH
CE Hold Time 0 0 0 ns
t
WLWH
t
WP
WE Pulse Width 40 40 40 ns
t
WHWL
t
WPH
WE High Pulse Width 20 20 20 ns
t
WHWH1
(2)
- Program Pulse Width 10 10 10 µs
t
WHWH2
(2)
- Erase Pulse Width 9.5 9.5 9.5 ms
t
WHGL
- Write Recovery Time Before Read 6 6 6 µs
t
GHWL
- Read Recovery Time Before Write 0 0 0 µs
t
VPEL
-V
PP
Setup Time to CE 100 100 100 ns
ERASE AND PROGRAMMING PERFORMANCE
(1)
28F512-90 28F512-12 28F512-15
Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Chip Erase Time
(3)(5)
0.5 10 0.5 10 0.5 10 sec
Chip Program Time
(3)(4)
16 16 16sec
Note:
(1) Please refer to Supply characteristics for the value of V
PPH
and V
PPL
. The V
PP
supply can be either hardwired or switched. If V
PP
is switched,
V
PPL
can be ground, less than V
CC
+ 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V
PP
.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.

CAT28F512G90

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
NOR Flash 64 X 8 512K 90ns
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union