© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 11
1 Publication Order Number:
MC10E195/D
MC10E195, MC100E195
5 V ECL Programmable
Delay Chip
Description
The MC10E/100E195 is a programmable delay chip (PDC)
designed primarily for clock de-skewing and timing adjustment. It
provides variable delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.
Because the delay programmability of the E195 is achieved by
purely differential ECL gate delays the device will operate at
frequencies of > 1.0 GHz while maintaining over 600 mV of output
swing.
The E195 thus offers very fine resolution, at very high frequencies,
that is selectable entirely from a digital input allowing for very
accurate system clock timing.
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
• 2.0 ns Worst Case Delay Range
• ≈ 20 ps/Delay Step Resolution
• > 1.0 GHz Bandwidth
• On Chip Cascade Circuitry
• PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ > 2 kV Human Body Model
♦ > 200 V Machine Model
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D
)
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
PLCC−28
FN SUFFIX
CASE 776−02
MCxxxE195FNG
AWLYYWW
1
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
ORDERING INFORMATION
• Flammability Rating: UL 94 V−0 @ 0.125 in
Oxygen Index: 28 to 34
• Transistor Count = 368 Devices
• These Devices are Pb-Free, Halogen Free
and are RoHS Compliant
See detailed ordering and shipping information on page 9
of this data sheet.
