MC10E195, MC100E195
www.onsemi.com
7
V
CCO
ADDRESS BUS (A0-A6)
A7
INPUT
D1
D0
LEN
V
EE
IN
IN
V
BB
D2
D3
D4
D5
D6
D7
EN
SET MIN
SET MAX
CASCADE
CASCADE
V
CC
V
CCO
Q
Q
D1
D0
LEN
V
EE
IN
IN
V
BB
EN
SET MIN
SET MAX
CASCADE
CASCADE
V
CC
V
CCO
Q
Q
V
CCO
OUTPUT
D2
D3
D4
D5
D6
D7
E195
Chip #1
E195
Chip #2
Figure 3. Cascading Interconnect Architecture
Cascading Multiple E195’s
To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195’s without the need for any
external gating. Furthermore this capability requires only
one more address line per added E195. Obviously cascading
multiple PDC’s will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
Figure 3 illustrates the interconnect scheme for cascading
two E195’s. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195
is the cascade control pin. With the interconnect scheme of
Figure 3 when D7 is asserted it signals the need for a larger
programmable range than is achievable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7
of chip #1 above is low the cascade output will also be low
while the cascade bar output will be a logical high. In this
condition the SET MIN pin of chip #2 will be asserted and
thus all of the latches of chip #2 will be reset and the device
will be set at its minimum delay. Since the RESET and SET
inputs of the latches are overriding any changes on the
A0−A6 address bus will not affect the operation of chip #2.
Chip #1 on the other hand will have both SET MIN and
SET MAX de-asserted so that its delay will be controlled
entirely by the address bus A0−A6. If the delay needed is
greater than can be achieved with 31.75 gate delays
(1111111 on the A0−A6 address bus) D7 will be asserted to
signal the need to cascade the delay to the next E195 device.
When D7 is asserted the SET MIN pin of chip #2 will be
de-asserted and the delay will be controlled by the A0−A6
address bus. Chip #1 on the other hand will have its SET
MAX pin asserted resulting in the device delay to be
independent of the A0−A6 address bus.
When the SET MAX pin of chip #1 is asserted the D0 and
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E195.
To expand this cascading scheme to more devices one
simply needs to connect the D7 input and CASCADE
outputs of the current most significant E195 to the new most
significant E195 in the same manner as pictured in Figure 3.
The only addition to the logic is the increase of one line to
the address bus for cascade control of the second PDC.
SET MIN
ET MAX
TO SELECT MULTIPLEXERS
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
D0 Q0
LEN
Reset Reset
D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5
D6 Q6 D7 Q7
LEN LEN LEN LEN LEN LEN LEN
CASCADE
CASCADE
Figure 4. Expansion of the Latch Section of the E195 Block Diagram
Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset
