TC58NVG2S0HTA00
2013-07-05C
6
AC TEST CONDITIONS
CONDITION
PARAMETER
V
CC
: 2.7 to 3.6V
Input level V
CC
− 0.2 V, 0.2 V
Input pulse rise and fall time 3 ns
Input comparison level Vcc / 2
Output data comparison level Vcc / 2
Output load C
L
(50 pF) + 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the BY/RY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
=
0 to 70
℃
, V
CC
=
2.7 to 3.6V)
SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
t
PROG
Average Programming Time ⎯ 300 700 µs
t
DCBSYW1
Data Cache Busy Time in Write Cache (following 11h) ⎯ ⎯ 10 µs
t
DCBSYW2
Data Cache Busy Time in Write Cache (following 15h) ⎯ ⎯ 700 µs (2)
N Number of Partial Program Cycles in the Same Page ⎯ ⎯ 4 (1)
t
BERASE
Block Erasing Time ⎯ 2.5 5 ms
(1) Refer to Application Note (12) toward the end of this document.
(2) t
DCBSYW2
depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.