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LTC3857IGN-1#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
LTC3857-1
10
38571fc
FUNCTIONAL DIAGRAM
SW
TOP
BOOST
TG
C
B
C
IN
D
D
B
PGND
BOT
BG
INTV
CC
INTV
CC
V
IN
C
OUT
V
OUT
38571 FD
R
SENSE
DROP
OUT
DET
BOT
TOP ON
S
R
Q
Q
SHDN
SLEEP
0.425V
ICMP
2.7V
0.55V
IR
3mV
SLOPE COMP
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
SENSE
+
SENSE
–
PGOOD1
V
FB1
0.88V
0.72V
L
+
–
+
–
FREQ
+
–
+
–
+
–
+
–
+
–
+
–
SWITCH
LOGIC
V
FB
R
A
C
C
R
C
C
C2
R
B
0.80V
TRACK/SS
0.88V
0.5µA
RUN
11V
I
TH
TRACK/SS
+
–
C
SS
1µA
SHDN
FOLDBACK
SHDN
RST
2(V
FB
)
PLLIN/MODE
20µA
VCO
LDO
EN
INTV
CC
5.1V
SYNC
DET
100k
CLK2
C
LP
CLK1
V
IN
EXTV
CC
LDO
PFD
EN
4.7V
5.1V
+
–
SGND
EA
OV
LTC3857-1
11
38571fc
OPERATION
(Refer to the Functional Diagram)
Main Control Loop
The LTC3857-1 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal op-
eration, each external top MOSFET is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, ICMP, resets the RS
latch. The peak inductor current at which ICMP trips and
resets the latch is controlled by the voltage on the I
TH
pin,
which is the output of the error amplifier, EA. The error
amplifier compares the output voltage feedback signal at
the V
FB
pin, (which is generated with an external resistor
divider connected across the output voltage, V
OUT
, to
ground) to the internal 0.800V reference voltage. When the
load current increases, it causes a slight decrease in V
FB
relative to the reference, which causes the EA to increase
the I
TH
voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTV
CC
/EXTV
CC
Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV
CC
pin. When
the EXTV
CC
pin is left open or tied to a voltage less than
4.7V, the V
IN
LDO (low dropout linear regulator) supplies
5.1V from V
IN
to INTV
CC
. If EXTV
CC
is taken above 4.7V,
the V
IN
LDO is turned off and an EXTV
CC
LDO is turned on.
Once enabled, the EXTV
CC
LDO supplies 5.1V from EXTV
CC
to INTV
CC
. Using the EXTV
CC
pin allows the INTV
CC
power
to be derived from a high efficiency external source such
as one of the LTC3857-1 switching regulator outputs.
Each top MOSFET driver is biased from the floating boot-
strap capacitor C
B
, which normally recharges during each
cycle through an external diode when the top MOSFET
turns off. If the input voltage, V
IN
, decreases to a voltage
close to V
OUT
, the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one-twelfth of the clock period every tenth cycle to
allow C
B
to recharge.
Shutdown and Start-Up (RUN1, RUN2 and
TRACK/ SS1, TRACK/SS2 Pins)
The two channels of the LTC3857-1 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either of
these pins below 1.26V shuts down the main control loop
for that controller. Pulling both pins below 0.7V disables
both controllers and most internal circuits, including the
INTV
CC
LDOs. In this state, the LTC3857-1 draws only 8µA
of quiescent current.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
higher voltage (for example, V
IN
), so long as the maximum
current into the RUN pin does not exceed 100µA.
The start-up of each controller’s output voltage V
OUT
is
controlled by the voltage on the TRACK/SS pin for that
channel. When the voltage on the TRACK/SS pin is less
than the 0.8V internal reference, the LTC3857-1 regulates
the V
FB
voltage to the TRACK/SS pin voltage instead of the
0.8V reference. This allows the TRACK/SS pin to be used
to program a soft-start by connecting an external capacitor
from the TRACK/SS pin to SGND. An internal 1µA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V (and beyond up to the absolute maximum
rating of 6V), the output voltage V
OUT
rises smoothly from
zero to its final value.
Alternatively the TRACK/SS pin can be used to cause the
start-up of V
OUT
to track that of another supply. Typically,
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see Ap-
plications Information section).
LTC3857-1
12
38571fc
OPERATION
(Refer to the Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3857-1 can be enabled to enter high efficiency
Burst Mode operation, constant frequency pulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to GND. To select forced continuous operation,
tie the PLLIN/MODE pin to INTV
CC
. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTV
CC
– 1.3V.
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to ap-
proximately 15% of the maximum sense voltage even
though the voltage on the I
TH
pin indicates a lower value.
If the average inductor current is higher than the load
current, the error amplifier, EA, will decrease the voltage
on the I
TH
pin. When the I
TH
voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The I
TH
pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3857-1 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3857-1 draws only 50µA of quiescent
current. If both channels are in sleep mode, the LTC3857-1
draws only 65µA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the I
TH
pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse cur-
rent comparator, IR, turns off the bottom external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the induc-
tor current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current is
determined by the voltage on the I
TH
pin, just as in normal
operation. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous opera-
tion has the advantage of lower output voltage ripple and
less interference to audio circuitry. In forced continuous
mode, the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3857-1 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3857-1’s controllers
can be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV
CC
or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects 535kHz. Placing a resistor between FREQ and
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LTC3857IGN-1#PBF

Mfr. #:
Buy LTC3857IGN-1#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low IQ, Dual, 2-Phase Synchronous Step Down Controller
Lifecycle:
New from this manufacturer.
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