DS563F2 13
CS5381
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode)
8. Power-Down Mode is defined as RST
= Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VL,VD = 5 V
VL,VD = 3.3 V
I
A
I
D
I
D
-
-
-
36
36
24
43
46
28
mA
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 8) VL,VD = 5 V
I
A
I
D
-
-
100
100
-
-
uA
uA
Power Consumption
(Normal Operation) VA, VL, VD = 5 V
VA = 5 V; VL, VD = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
360
260
1
445
307
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 9)
PSRR - 65 - dB
V
Q
Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
2.5
25
0.01
-
-
-
V
k
mA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
5
4.5
0.01
-
-
-
V
k
mA
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VL)
V
IH
70% - - V
Low-Level Input Voltage (% of VL)
V
IL
--30%V
High-Level Output Voltage at I
o
= 100 µA (% of VL)
V
OH
70% - - V
Low-Level Output Voltage at I
o
= 100 µA (% of VL)
V
OL
--15%V
OVFL Current Sink
I
ovfl
--4.0mA
Input Leakage Current
I
in
-10 - 10 µA
Parameter Symbol Min Typ Max Unit
Allowable Junction Temperature
--135°C
Junction to Ambient Thermal Impedance
(Multi-layer PCB) TSSOP
(Multi-layer PCB) SOIC
(Single-layer PCB) TSSOP
(Single-layer PCB) SOIC
θ
JA-TM
θ
JA-SM
θ
JA-TS
θ
JA-SS
-
-
-
-
70
60
105
80
-
-
-
-
°C/W
°C/W
°C/W
°C/W
14 DS563F2
CS5381
TYPICAL CONNECTION DIAGRAM
FILT+
AINL+
AINL-
V
D
0.01
µ
F
A/D CONVERTER
SCLK
CS5381
M/S
MCLK
AINR+
AINR-
VQ
**47
µ
F
+
RST
VA V
L
+5V
1
µ
F
+5Vto 2.5 V
5.1
1
µ
F
+
+ +
SDOUT
GND
I
2
S/LJ
LRCK
GND
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.01
µ
F
0.01
µ
F
0.01
µF
HPF
M0
M1
REFGND
MDIV
+5 V to 3.3 V
1
µ
F 0.01
µF
1
µ
F
+
Analog
Input
Buffer
(Figure 24)
Analog
Input
Buffer
(Figure 24)
OVFL
10 k
VL
*
0.01
µ
F
** Capacitor value
affects low frequency
distortion. See
Section 3.9.
* Resistor may only
be used if VD is
derived from VA. If
used, do not drive any
other logic from VD.
Figure 22. Typical Connection Diagram
DS563F2 15
CS5381
3. APPLICATIONS
3.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 1.
3.2 System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-
ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.
3.2.1 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 23. Refer to Table 2 for common master clock frequencies.
M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)
00
Single-Speed Mode 2 kHz - 54 kHz
01
Double-Speed Mode 50 kHz - 108 kHz
10
Quad-Speed Mode 100 kHz - 216 kHz
11
Reserved
Table 1. CS5381 Mode Control
÷ 128
÷ 256
÷ 64
M0M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 1
0
1
MCLK
MDIV
Figure 23. CS5381 Master Mode Clocking

CS5381-KSZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs 120dB 192kHz Multi-Bit ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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