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AD7450ARZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
AD7450
–3–
Parameter Conditions/Comments A Version B Version Unit
CONVERSION RATE
Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK Cycles
1.07 µs with a 15 MHz SCLK
Track-and-Hold Sine Wave Input 200 200 ns max
Acquisition Time
3, 8
Throughput Rate
9
V
DD
= 5 V 1 1 MSPS max
V
DD
= 3 V 833 833 kSPS max
POWER REQUIREMENTS
V
DD
Range: 3 V ± 10%; 5 V ± 5% 3/5 3/5 V min/max
I
DD
10, 11
Normal Mode (Static) V
DD
= 3 V/5 V SCLK; ON or OFF 0.5 0.5 mA typ
Normal Mode (Operational) V
DD
= 5 V; f
SAMPLE
= 1 MSPS 1.8 1.8 mA max
V
DD
= 3 V; f
SAMPLE
= 833 kSPS 1.25 1.25 mA max
Full Power-Down Mode SCLK ON or OFF 1 1 µA max
Power Dissipation
Normal Mode (Operational) V
DD
= 5 V; f
SAMPLE
= 1 MSPS; 9 9 mW max
1.38 mW typ for 100 KSPS
10
V
DD
= 3 V; f
SAMPLE
= 833 kSPS; 3.75 3.75 mW max
0.53 mW typ for 100 KSPS
10
Full Power-Down Mode V
DD
= 5 V; SCLK ON or OFF 5 5 µW max
V
DD
= 3 V; SCLK ON or OFF 3 3 µW max
NOTES
1
Temperature range is as follows: A and B Versions: –40°C to +85°C.
2
Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9.
3
See Terminology section.
4
A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto V
DD
. A 2.2 nF capacitor is used to decouple V
DD
to GND.
5
If the input spans of V
IN+
and V
IN–
are both V
REF
, and they are 180° out of phase, the differential voltage is 2 ⫻ V
REF
.
6
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 5 V, the reference can range up to 3.5 V (see References section).
7
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 3 V, the reference can range up to 2.2 V (see References section).
8
Sample tested @ 25°C to ensure compliance.
9
See Serial Interface section.
10
See Power Versus Throughput Rate section.
11
Measured with a midscale dc input.
Rev. A
–4–
AD7450
Limit at T
MIN
, T
MAX
Parameter 3 V 5 V Unit Description
f
SCLK
4
50 50 kHz min
15 18 MHz max
t
CONVERT
16 ⫻ t
SCLK
16 ⫻ t
SCLK
t
SCLK
= 1/f
SCLK
1.07 0.88 µs max SCLK = 15 MHz, 18 MHz
t
QUIET
25 25 ns min Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of
CS
t
1
10 10 ns min Minimum
CS
Pulsewidth
t
2
10 10 ns min
CS
Falling Edge to SCLK Falling Edge Setup Time
t
3
5
20 20 ns max Delay from
CS
Falling Edge until SDATA Three-State Disabled
t
4
5
40 40 ns max Data Access Time after SCLK Falling Edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK High Pulsewidth
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK Low Pulsewidth
t
7
10 10 ns min SCLK Edge to Data Valid Hold Time
t
8
6
10 10 ns min SCLK Falling Edge to SDATA Three-State Enabled
35 35 ns max SCLK Falling Edge to SDATA Three-State Enabled
t
POWER-UP
7
11µs max Power-Up Time from Full Power-Down
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 1 and the Serial Interface section.
3
Common-mode voltage.
4
Mark/space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V, and the time for an output to cross
0.4 V
or 2.0 V for V
DD
= 3 V.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
See Power-Up Time section.
Specifications subject to change without notice.
1 2 345 13 161514
00 00DB11 DB10 DB2 DB1
DB0
t
2
4 LEADING ZEROS
t
8
t
QUIET
t
CONVERT
CS
SCLK
SDATA
t
6
t
7
t
4
t
5
t
3
t
1
THREE-STATE
Figure 1. Serial Interface Timing Diagram
TIMING SPECIFICATIONS
1, 2
(V
DD
= 2.7 V to 3.3 V, f
SCLK
= 15 MHz, f
S
= 833 kSPS, V
REF
= 1.25 V; V
DD
= 4.75 V to 5.25 V,
f
SCLK
= 18 MHz, f
S
= 1 MSPS, V
REF
= 2.5 V; V
CM
3
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Rev. A
AD7450
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to
avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
IN+
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
IN–
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . ±10 mA
Operating Temperature Range
Commercial (A and B Version) . . . . . . . . . –40
o
C to +85
o
C
Storage Temperature Range . . . . . . . . . . . . –65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW
␪
JA
Thermal Impedance . . . . . . . . . . . . . . . . 157°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9°C/W (µSOIC)
␪
JC
Thermal Impedance . . . . . . . . . . . . . . . . . 56°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74°C/W (µSOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215
o
C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
o
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
NOTES
1
Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
TO
OUTPUT
PIN
C
L
50pF
1.6V
200A
I
OL
200A
I
OH
Figure 2. Load Circuit for Digital Output Timing
Specifications
Rev. A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

AD7450ARZ-REEL7

Mfr. #:
Buy AD7450ARZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V DIFF INPUT 12 BIT SAR IC
Lifecycle:
New from this manufacturer.
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