–6–
AD7450
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
V
REF
V
IN+
V
IN–
V
DD
SCLK
SDATA
CS
GND
AD7450
PIN FUNCTION DESCRIPTION
Pin Number Mnemonic Function
1V
REF
Reference Input for the AD7450. An external reference must be applied to this input. For a
5 V power supply, the reference is 2.5 V (± 1%), and for a 3 V power supply, the reference is
1.25 V (± 1%) for specified performance. This pin should be decoupled to GND with a
capacitor of at least 0.1 µF. See the References section for more details.
2V
IN+
Positive Terminal for Differential Analog Input
3V
IN–
Negative Terminal for Differential Analog Input
4 GND Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input
signals and any external reference signal should be referred to this GND voltage.
5 CS Chip Select. Active low logic input. This input provides the dual function of initiating a
conversion on the AD7450 and framing the serial data transfer.
6 SDATA Serial Data. Logic output. The conversion result from the AD7450 is provided on this
output as a serial data stream. The bits are clocked out on the falling edge of the SCLK
input. The data stream consists of four leading zeros followed by the 12 bits of conversion
data that is provided MSB first. The output coding is two’s complement.
7 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7450’s conversion process.
8V
DD
Power Supply Input. V
DD
is 3 V (± 10%) or 5 V (± 5%). This supply should be decoupled to
GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Rev. A
AD7450
–7–
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
S
/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal–to–(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7450, it is defined as:
THD dB
VVVVV
V
()=
++++
20
2
2
3
2
4
2
5
2
6
2
1
log
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second to the sixth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2, or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
The AD7450 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is reduced
by 0.1 dB or 3 dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power
of a 200 mV p-p sine wave applied to the common-mode volt-
age of V
IN+
and V
IN–
of frequency fs:
CMRR dB Pf Pfs() log ( / )= 10
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero Code Error
This is the deviation of the midscale code transition (111...111
to 000...000) from the ideal V
IN+
– V
IN–
(i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V
IN+
– V
IN–
(i.e., +V
REF
– 1 LSB),
after the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal V
IN+
– V
IN–
(i.e., –V
REF
+ 1 LSB), after
the zero code error has been adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time re-
quired for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the ap-
plied input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power
of a 200 mV p-p sine wave applied to the ADC V
DD
supply of
frequency f
S
.
PSRR dB log Pf /Pfs() ( )= 10
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Rev. A
–8–
AD7450–Typical Performance Characteristics
FREQUENCY – kHz
SNR – dBs
0
–60
–120
050 500100 150 200 250 300 350 400 450
–20
–40
–80
–100
8192 POINT FFT
f
SAMPLE
= 1MSPS
f
IN
= 300kHz
SINAD = 71.7dB
THD = –82.8dB
PK NOISE = –85.3dB
TPC 1. Dynamic Performance at
1 MSPS with V
DD
= 5 V
CODE
DNL ERROR – LSB
1.0
0.4
–0.2
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0
0 1024 2048 3072 4096
TPC 4. Typical Differential
Nonlinearity (DNL) V
DD
= 5 V
CODE
INL ERROR – LSB
1.0
0.4
–0.2
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0
0 1024 2048 3072 4096
TPC 7. Typical Integral
Nonlinearity (INL) V
DD
= 3 V
FREQUENCY – kHz
SNR – dBs
0
–60
–120
050100 150 200 250 300 350
–20
–40
–80
–100
8192 POINT FFT
f
SAMPLE
= 833kSPS
f
IN
= 300kHz
SINAD = 70.2dB
THD = –82dB
PK NOISE = –87.1dB
TPC 2. Dynamic Performance at
833 kSPS with V
DD
= 3 V
CODE
DNL ERROR – LSB
1.0
0.4
–0.2
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0
0 1024 2048 3072 4096
TPC 5. Typical Differential
Nonlinearity (DNL) V
DD
= 3 V
1.0
0.5
0
–0.5
–1.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
CHANGE IN DNL-LSB
V
REF
POSITIVE DNL
NEGATIVE DNL
TPC 8. Change in DNL vs. Reference
Voltage V
DD
= 5 V
INPUT FREQUENCY – kHz
SINAD – dB
–63
–75
–69
–65
–67
–71
–73
10 100 1000
V
DD
= 4.75V
V
DD
= 2.7V
V
DD
= 3.3V
V
DD
= 5.25V
TPC 3. SINAD vs. Analog Frequency
for Various Supply Voltages
CODE
INL ERROR – LSB
1.0
0.4
–0.2
0.8
0.6
0.2
0
–0.4
–0.6
–0.8
–1.0
0 1024 2048 3072 4096
TPC 6. Typical Integral
Nonlinearity (INL) V
DD
= 5 V
V
REF
1.0
0.5
–1.0
0
–0.5
1.5
CHANGE IN DNL-LSB
0 0.6 1.2 1.8 2.4
POSITIVE DNL
NEGATIVE DNL
TPC 9. Change in DNL vs. Reference
Voltage V
DD
= 3.3 V*
(Default Conditions: T
A
= 25C)
Rev. A

AD7450ARZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V DIFF INPUT 12 BIT SAR IC
Lifecycle:
New from this manufacturer.
Delivery:
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