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NL17SZ74USG

P1-P3P4-P6
NL17SZ74
www.onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Symbo
l
Parameter V
CC
(V) Test Conditions
T
A
= 25°C T
A
= −55 to 125°C
Units
Min Typ Max Min Max
f
MAX
Maximum Clock
Frequency
(50% Duty Cycle)
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
75 75
MHz
2.5 ± 0.2 150 150
3.3 ± 0.3 200 200
5.0 ± 0.5 250 250
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
175 175
5.0 ± 0.5 200 200
t
PLH
,
t
PHL
Propagation Delay,
CP to Q or Q
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
2.5 6.5 12.5 2.5 13
ns
2.5 ± 0.2 1.5 3.8 7.5 1.5 8.0
3.3 ± 0.3 1.0 2.8 6.5 1.0 7.0
5.0 ± 0.5 0.8 2.2 4.5 0.8 5.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
1.0 3.4 7.0 1.0 7.5
5.0 ± 0.5 1.0 2.6 5.0 1.0 5.5
t
PLH
,
t
PHL
Propagation Delay,
PR
or CLR to Q or Q
(Waveform 2)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
2.5 6.5 14 2.5 14.5
ns
2.5 ± 0.2 1.5 3.8 9.0 1.5 9.5
3.3 ± 0.3 1.0 2.8 6.5 1.0 7.0
5.0 ± 0.5 0.8 2.2 5.0 0.8 5.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
1.0 3.4 7.0 1.0 7.5
5.0 ± 0.5 1.0 2.6 5.0 1.0 5.5
t
S
Setup Time, D to CP
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
6.5 6.5
ns
2.5 ± 0.2 3.5 3.5
3.3 ± 0.3 2.0 2.0
5.0 ± 0.5 1.5 1.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
2.0 2.0
5.0 ± 0.5 1.5 1.5
t
H
Hold Time, D to CP
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
0.5 0.5
ns
2.5 ± 0.2 0.5 0.5
3.3 ± 0.3 0.5 0.5
5.0 ± 0.5 0.5 0.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
0.5 0.5
5.0 ± 0.5 0.5 0.5
t
W
Pulse Width,
CP, CLR
, PR
(Waveform 3)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
6.0 6.0
ns
2.5 ± 0.2 4.0 4.0
3.3 ± 0.3 3.0 3.0
5.0 ± 0.5 2.0 2.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
3.0 3.0
5.0 ± 0.5 2.0 2.0
t
REC
Recover Time
PR
; CLR to CP
(Waveform 3)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
8.0 8.0
ns
2.5 ± 0.2 4.5 4.5
3.3 ± 0.3 3.0 3.0
5.0 ± 0.5 3.0 3.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
3.0 3.0
5.0 ± 0.5 3.0 3.0
8. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/2 (per flip−flop). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
CAPACITANCE (Note 9)
Symbol
Parameter Condition Typical Unit
C
IN
Input Capacitance V
CC
= 5.5 V 7.0 pF
C
OUT
Output Capacitance V
CC
= 5.5 V 7.0 pF
C
PD
Power Dissipation Capacitance (Note 10)
Frequency = 10 MHz
V
CC
= 3.3 V
V
CC
= 5.0 V
16
21
pF
9. T
A
= +25°C, f = 1 MHz
10.C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at
no output loading and operating at 50% duty cycle. (See Figure 1) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
= C
PD
V
CC
f
in
+ I
CC(static)
.
NL17SZ74
www.onsemi.com
5
t
rec
WAVEFORM 3 − RECOVERY TIME
t
R
= t
F
= 3.0 ns from 10% to 90%; f = 1 MHz; t
w
= 500 ns
Output Reg: V
OL
≤ 0.8 V, V
OH
≥ 2.0 V
Vcc
0 V
Vcc
0 V
50%
50%
Figure 1. AC Waveforms
WAVEFORM 2 − PROPAGATION DELAYS
t
R
= t
F
= 3.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
PR
, CLR
CP
Vcc
0 V
PR
CLR
50%
Q
Vcc
0 V
V
OH
50%
Q
V
OL
50%
50%
50%
t
PLH
t
PHL
t
PHL
t
PLH
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
t
R
= t
F
= 3.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
Vcc
0 V
D
CP
50%
Q,
Q
Vcc
0 V
V
OH
V
OL
t
PLH
, t
PHL
t
h
t
s
50%
50%
f
max
t
w
t
w
t
w
50%
PULSE
GENERATOR
R
T
DUT
V
CC
R
L
C
L
Figure 2. Test Circuit
NL17SZ74
www.onsemi.com
6
PACKAGE DIMENSIONS
US8
US SUFFIX
CASE 493−02
ISSUE B
DIM
A
MIN MAX MIN MAX
INCHES
1.90 2.10 0.075 0.083
MILLIMETERS
B 2.20 2.40 0.087 0.094
C 0.60 0.90 0.024 0.035
D 0.17 0.25 0.007 0.010
F 0.20 0.35 0.008 0.014
G 0.50 BSC 0.020 BSC
H 0.40 REF 0.016 REF
J 0.10 0.18 0.004 0.007
K 0.00 0.10 0.000 0.004
L 3.00 3.20 0.118 0.126
M 0 6 0 6
N 5 10 5 10
P 0.23 0.34 0.010 0.013
R 0.23 0.33 0.009 0.013
S 0.37 0.47 0.015 0.019
U 0.60 0.80 0.024 0.031
V 0.12 BSC
0.005 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
LB
A
P
G
41
58
C
K
D
SEATING
J
S
R
U
DETAIL E
V
F
H
N
R 0.10 TYP
M
−Y−
−X−
−T−
DETAIL E
T
M
0.10 (0.004) XY
T0.10 (0.004)
____
____
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ǒ
mm
inches
Ǔ
SCALE 8:1
3.8
0.015
0.50
0.0197
1.0
0.0394
0.30
0.012
1.8
0.07
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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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P
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NL17SZ74/D
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P1-P3P4-P6

NL17SZ74USG

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Description:
Flip Flops 1.65-5.5V CMOS Single D-Type
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