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5962-8770102RA

P1-P3P4-P6P7-P9
PLCC
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
V
REF
A
DGND
DAC A/DAC B
(MSB) DB7
DB6
V
REF
B
V
DD
WR
CS
DB0 (LSB)
AD7528
R
FB
A
OUT A
AGND
OUT B
R
FB
B
DB5
DB4
DB3
DB2
DB1
V
DD
= +5 V V
DD
= +15 V
Parameter Version
1
T
A
= +25°CT
MIN
, T
MAX
T
A
= +25°CT
MIN
, T
MAX
Units Test Conditions/Comments
CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111.
V
REF
A to OUT B All –77 –77 dB typ V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
B = 0 V see Figure 6.
V
REF
B to OUT A –77 –77 dB typ V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
A = 0 V see Figure 6.
DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to
11111111
HARMONIC DISTORTlON All –85 –85 dB typ V
IN
= 6 V rms @ 1 kHz
NOTES
1
Temperature Ranges are J, K, L Versions: –40°C to +85°C
A, B, C Versions: –40°C to +85°C
S, T, U Versions: –55°C to +125°C
2
Specifications applies to both DACs in AD7528.
3
Guaranteed by design but not production tested.
4
Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.
5
These characteristics are for design guidance only and are not subject to test.
6
Feedthrough can be further reduced by connecting the metal lid on the ceramic package
(suffix D) to DGND.
Specifications subject to change without notice.
AD7528, ideal maximum output is V
REF
– 1 LSB. Gain error of
both DACs is adjustable to zero with external resistance.
Output Capacitance
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V
REF
A,
V
REF
B = AGND.
Propagation Delay
This is a measure of the internal delays of the circuit and is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.
Channel-to-Channel Isolation
The proportion of input signal from one DAC’s reference input
which appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
PIN2
, V
PIN20
to AGND . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
A, V
REF
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
V
RFB
A, V
RFB
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C
Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C
Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
CAUTION:
1. ESD sensitive device. The digital control inputs are diode
protected; however, permanent damage may occur on uncon-
nected devices subjected to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts.
2. Do not insert this device into powered sockets. Remove
power before insertion or removal.
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For the
AD7528
REV. B
–3–
DIP, SOIC
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7528
DB4
DB5
DB6
OUT A
R
FB
A
V
REF
A
(MSB) DB7
DAC A/DAC B
DGND
DB3
DB2
DB1
R
FB
B
V
REF
B
V
DD
DB0 (LSB)
CS
WR
AGND
OUT B
AD7528
REV. B–4–
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The con-
trol input DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection:
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode:
The selected DAC latch retains the data which was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/DAC B CS WR DAC A DAC B
L L L WRITE HOLD
H L L HOLD WRITE
X H X HOLD HOLD
X X H HOLD HOLD
L = Low State; H = High State; X = Don’t Care.
WRITE CYCLE TIMING DIAGRAM
V
DD
t
DH
V
IH
V
IL
t
DS
t
WR
t
AS
t
AH
t
CS
t
CH
V
DD
V
DD
V
DD
0
0
0
0
CHIP SELECT
DAC A/DAC B
WRITE
DATA IN
(DB0 – DB7)
DATA IN STABLE
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED
FROM 10% TO 90% OF V
DD
.
V
DD
=
+5V, t
r
=
t
f
= 20ns;
V
DD
=
+15V, t
r
=
t
f
= 40ns;
2. TIMING MEASUREMENT REFERENCE LEVEL IS
V
IH
+ V
IL
2
CIRCUIT INFORMATION—D/A SECTION
The AD7528 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steer-
ing switches. A simplified D/A circuit for DAC A is shown in
V
REF
A
AGND
DAC A DATA LATCHES
AND DRIVERS
2R
S1
2R
S2
2R
S3
2R
S8
2R
RRR
OUT A
R
FB
A
R
Figure 1. Simplified Functional Circuit for DAC A
Figure 1. An inverted R-2R ladder structure is used, that is, bi-
nary weighted currents are switched between the DAC output
and AGND thus maintaining fixed currents in each ladder leg
independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of the
AD7528’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor R
O
as shown in Figure
2 is the equivalent output resistance of the device which varies
with input code (excluding all 0s code) from 0.8 R to 2 R. R is
typically 11 kΩ. C
OUT
is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF depending
upon the digital input. g(V
REF
A, N) is the Thevenin equivalent
voltage generator due to the reference input voltage V
REF
A and
the transfer function of the R-2R ladder.
R
FB
A
AGND
OUT A
R
O
g(V
REF
A, N)
I
LKG
C
OUT
R
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS inverters designed such
that when the AD7528 is operated with V
DD
= 5 V, the buffer
converts TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When V
IN
is in the region of 2.0 volts to 3.5 volts the
input buffers operate in their linear region and pass a quiescent
current, see Figure 3. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (V
DD
and DGND) as is practically possible.
The AD7528 may be operated with any supply voltage in the
range 5 ≤ V
DD
≤ 15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
V
IN
– Volts
800
0
I
DD
mA (V
DD
= +5V)
1 2 3 4 5 6 7 8 9 10 11 13 1412
700
600
500
400
300
200
100
I
DD
mA (V
DD
= +15V)
9
8
7
6
5
4
3
2
1
V
DD
= +5V
V
DD
= +15V
T
A
= +258C
ALL DIGITAL INPUTS
TIED TOGETHER
Figure 3. Typical Plots of Supply Current, I
DD
vs. Logic
Input Voltage V
IN
, for V
DD
= +5 V and +15 V
AD7528
REV. B –5–
Table I. Unipolar Binary Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
–V
IN
255
256
1 0 0 0 0 0 0 1
–V
IN
129
256
1 0 0 0 0 0 0 0
–V
IN
128
256
=−
V
IN
2
0 1 1 1 1 1 1 1
–V
IN
127
256
0 0 0 0 0 0 0 1
–V
IN
1
256
0 0 0 0 0 0 0 0
–V
IN
0
256
= 0
Note: 1 LSB =
2
−8
()
V
IN
()
=
1
256
V
IN
()
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
+V
IN
127
128
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
–V
IN
1
128
0 0 0 0 0 0 0 1
–V
IN
127
128
0 0 0 0 0 0 0 0
–V
IN
128
128
Note: 1 LSB =
2
−7
()
V
IN
()
=
1
128
V
IN
()
Table III. Recommended Trim Resistor
Values vs. Grade
Trim
Resistor J/A/S K/B/T L/C/U
R1; R3 1 k 500 200
R2; R4 330 150 82
V
IN
A
(± 10V)
AD7528
V
IN
B
(± 10V)
R
FB
B
AGND
V
DD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT B
LATCH
R4
1
DAC B
C2
2
R3
1
DAC A
LATCH
V
OUT
B
AGND
R
FB
A
OUT A
R2
1
C1
2
V
OUT
A
AGND
R1
1
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2
C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 4. Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
V
IN
A
(± 10V)
AD7528
V
IN
B
(± 10V)
R
FB
B
AGND
V
DD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT BLATCH
R4
1
DAC B
C2
3
R3
1
DAC A
LATCH
V
OUT
B
AGND
R
FB
A
OUT A
R2
1
C1
3
V
OUT
A
AGND
R1
1
A1
R7
2
10kV
R6
2
20kV
A2
R5
20kV
R11
5kV
AGND
R10
2
20kV
R9
2
10kV
A4
R8
20kV
R12
5kV
AGND
A3
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR V
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR V
OUT
B = 0V WITH CODE 10000000 IN DAC B LATCH.
2
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3
C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 5. Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II
P1-P3P4-P6P7-P9

5962-8770102RA

Mfr. #:
Buy 5962-8770102RA
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 8-Bit Buffered Multiplying
Lifecycle:
New from this manufacturer.
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