5962-8770102RA

AD7528
REV. B–6–
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7528 specifi-
cations, careful attention must be given to the following points:
1. GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7528 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7528. In more
complex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7528 AGND and DGND
pins (1N914 or equivalent).
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which in turn causes a
code-dependent amplifier noise gain. The effect is a code-
dependent differential nonlinearity term at the amplifier
output which depends on V
OS
(V
OS
is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier V
OS
be no greater than 10% of
1 LSB over the temperature range of interest.
3. HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7528 will
depend upon the gain and phase characteristics of the output
amplifiers together with the optimum choice of the PC board
layout and decoupling components. Figure 6 shows the relation
INPUT FREQUENCY – Hz
–100
ISOLATION – dB
20k 50k 100k 200k 1M500k
–90
–80
–70
–60
–50
T
A
= +258C
V
DD
= +15V
V
IN
= 20V PEAK TO PEAK
Figure 6. Channel-to-Channel Isolation
AGND
V+
V–
AD644
V
REF
B*
V
DD
CS
LSB
C1 LOCATION
C2 LOCATION
V
REF
A*
DGND
DAC A/DAC B
MSB
PIN 8 OF TO-5 CAN (AD644)
AD7528 PIN 1
WR
AD7528
*NOTE
INPUT SCREENS
TO REDUCE
FEEDTHROUGH.
LAYOUT SHOWS
COPPER SIDE
(i.e., BOTTOM VIEW).
Figure 7. Suggested PC Board Layout for AD7528 with
AD644 Dual Op Amp
ship between input frequency and channel to channel isolation.
Figure 7 shows a printed circuit layout for the AD7528 and the
AD644 dual op amp which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7528 DAC R-2R ladder termination resistors are con-
nected to AGND within the device. This arrangement is par-
ticularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and V
DD
. Figure
8 shows a circuit which provides two +5 V to +8 V analog out-
puts by biasing AGND +5 V up from DGND. The two DAC
reference inputs are tied together and a reference input voltage
is obtained without a buffer amplifier by making use of the
constant and matched impedances of the DAC A and DAC B
reference inputs. Current flows through the two DAC R-2R
ladders into R1 and R1 is adjusted until the V
REF
A and V
REF
B
inputs are at +2 V. The two analog output voltages range from
+5 V to +8 V for DAC codes 00000000 to 11111111.
V
OUT
A = +5V TO +8V
V
DD
DATA
INPUTS
DAC A/DAC B
CS
WR
GND
V
DD
= +15V
SUGGESTED
OP AMP:
AD644
V
OUT
B = +5V TO +8V
R1
10kV
2 VOLTS
R2
1kV
AD584J
AD7528
DB0
DB7
DAC A
DAC B
Figure 8. AD7528 Single Supply Operation
Figure 9 shows DAC A of the AD7528 connected in a positive
reference, voltage switching mode. This configuration is useful
in that V
OUT
is the same polarity as V
IN
allowing single supply
operation. However, to retain specified linearity, V
IN
must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance, see Figure 10. Note that the input voltage is
connected to the DAC OUT A and the output voltage is taken
from the DAC V
REF
A pin.
V
REF
A
V
IN
(0V TO +2.5V)
V
DD
+15V
AD7528
DAC A
OUT A
V
OUT
Figure 9. AD7528 in Single Supply, Voltage Switching Mode
V
IN
A – Volts
3
2.5
ERROR – LSB
3.534567
2
1
T
A
= +258C
V
DD
= +15V
4.5 5.5 6.5 7.5
NONLINEARITY
DIFFERENTIAL
NONLINEARITY
Figure 10. Typical AD7528 Performance in Single Supply
Voltage Switching Mode (K/B/T, L/C/U Grades)
AD7528
REV. B –7
CIRCUIT EQUATIONS
CCRRR R121245== =,,
f
RC
Q
R
R
R
R
A
R
R
C
F
FBB
O
F
S
=
=
1
211
3
4
1
π
NOTE
DAC Equivalent Resistance
Equals
256 ×()DAC Ladder sis ce
DAC Digital Code
R
e tan
MICROPROCESSOR INTERFACE
ADDRESS BUS
A**
A + 1**
ADDRESS
DECODE
LOGIC
DAC A/DAC B
CS
DAC A
DB0
DB7
WR
V
MA
f2
AD7528*
DAC B
DATA BUS
D0–D7
A0–A15
CPU
6800
*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
**A = DECODED 7528 ADDR DAC A
A + 1 = DECODED 7528 ADDR DAC B
Figure 11. AD7528 Dual DAC to 6800 CPU Interface
ADDRESS BUS
A**
A + 1**
DAC A/DAC B
CS
DAC A
DB0
DB7
WR
AD7528*
DAC B
ADDR/DATA BUS
AD0–AD7
A8–A15
CPU
8085
*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
**A = DECODED 7528 ADDR DAC A
A + 1 = DECODED 7528 ADDR DAC B
NOTE:
8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE
BOTH DACs WITH DATA FROM H AND L REGISTERS
ADDRESS
DECODE
LOGIC
LATCH
8212
WR
ALE
Figure 12. AD7528 Dual DAC to 8085 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
V
REF
A
R
FB
A
V
CC
DATA
INPUTS
DAC A/DAC B
CS
WR
PASS/FAIL
OUTPUT
1kV
AD7528
DB0
DB7
DAC A
DAC B
OUT A
V
DD
V
REF
B
+V
REF
R
FB
B
3
2
7
AD311
COMPARATOR
OUT B
3
2
7
AD311
COMPARATOR
TEST INPUT
0 TO –V
REF
Figure 13. Digitally Programmable Window Comparator
(Upper and Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
In this state variable or universal filter configuration (Figure 14)
DACs A1 and B1 control the gain and Q of the filter character-
istic while DACs A2 and B2 control the cutoff frequency, f
C
.
DACs A2 and B2 must track accurately for the simple expres-
sion for f
C
to hold. This is readily accomplished by the AD7528.
Op amps are 2 × AD644. C3 compensates for the effects of op
amp gain bandwidth limitations.
DAC A/DAC B
CS WR
V
IN
V
DD
DB0–DB7
DATA 1
DAC B1
R
F
AD7528
DAC A/DAC B
CS WR
A3
V
DD
DB0–DB7
DATA 2
AD7528
A2
A1
R3
10kV
DAC A1
R
S
DAC A2
R1
HIGH
PASS
OUTPUT
R4
30kV
R5
30kV
C3
47pF
C1
1000pF
DAC B2
R2
A4
C2
1000pF
LOW
PASS
OUTPUT
BAND
PASS
OUTPUT
Figure 14. Digitally Controlled State Variable Filter
The filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor
control of filter parameters is required, e.g., equalizer, tone
controls, etc.
Programmable range for component values shown is f
C
= 0 kHz
to 15 kHz and Q = 0.3 to 4.5.
In the circuit of Figure 13 the AD7528 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed
limits, the pass/fail output will indicate a fail (logic zero).
AD7528
REV. B–8–
C681e–0–9/98
PRINTED IN U.S.A.
DIGITALLY CONTROLLED DUAL TELEPHONE
ATTENUATOR
In this configuration the AD7528 functions as a 2-channel digi-
tally controlled attenuator. Ideal for stereo audio and telephone
signal level control applications. Table IV gives input codes vs.
attenuation for a 0 dB to 15.5 dB range.
Input Code = 256 10 exp
Attenuation dB,
20
V
IN
B
V
OUT
A
V
IN
A
DATA BUS
DAC A/DAC B
CS
WR
AD7528
DB0
DB7
DAC A
DAC B
V
DD
V
OUT
B
A1
A2
SUGGESTED
OP AMP: AD644
Figure 15. Digitally Controlled Dual Telephone Attenuator
Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit
of Figure 15
Attn. DAC Input Code In Attn. DAC Input Code In
dB Code Decimal dB Code Decimal
0.0 1 1 1 1 1 1 1 1 255 88.0 0 1 1 0 0 1 1 0 102
0.5 1 1 1 1 0 0 1 0 242 88.5 0 1 1 0 0 0 0 0 96
1.0 1 1 1 0 0 1 0 0 228 89.0 0 1 0 1 1 0 1 1 91
1.5 1 1 0 1 0 1 1 1 215 89.5 0 1 0 1 0 1 1 0 86
2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81
2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76
3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72
3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68
4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64
4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61
5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57
5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54
6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51
6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48
7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46
7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43
For further applications information the reader is referred to
Analog Devices Application Note on the AD7528.
20-Lead Cerdip (Q-20)
0.97 (24.64)
0.935 (23.75)
SEATING
PLANE
0.02 (0.5)
0.016 (0.41)
0.07 (1.78)
0.05 (1.27)
0.15 (3.8)
0.125 (3.18)
0.20 (5.0)
0.14 (3.56)
0.11 (2.79)
0.09 (2.28)
20
110
11
0.28 (7.11)
0.24 (6.1)
PIN 1
0.14 (3.56)
0.125 (3.17)
158
08
0.32 (8.128)
0.29 (7.366)
0.011 (0.28)
0.009 (0.23)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP (N-20)
SEATING
PLANE
0.021 (0.533)
0.015 (0.381)
0.065 (1.66)
0.045 (1.15)
0.11 (2.79)
0.09 (2.28)
0.145 (3.683)
MIN
0.125 (3.175)
MIN
20
110
11
PIN 1
1.07 (27.18) MAX
0.255 (6.477)
0.245 (6.223)
0.32 (8.128)
0.30 (7.62)
0.011 (0.28)
0.009 (0.23)
0.135 (3.429)
0.125 (3.17)
158
08
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
20-Lead SOIC (R-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
88
08
0.0291 (0.74)
0.0098 (0.25)
3 458
11
20
10
1
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
20-Lead Plastic Leaded Chip Carrier (P-20A)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.180 (4.47)
0.165 (4.19)
0.12 (3.05)
0.09 (2.29)
0.020 (0.51) MIN
0.025 (0.64)
MIN
0.060 (1.53)
MIN
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.356 (9.04)
0.350 (8.89)
SQ
0.048 (1.21)
0.042 (1.07)
0.02
(0.51)
MAX
0.050
(1.27)
BSC
0.02 (0.51)
MAX
0.395 (10.02)
0.385 (9.78)
SQ

5962-8770102RA

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 8-Bit Buffered Multiplying
Lifecycle:
New from this manufacturer.
Delivery:
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