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93V857BG-025LFT

P1-P3P4-P6P7-P9P10-P11
4
ICS93V857-XXX
0693M—02/19/09
Recommended Operating Condition
(see note1)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DDQ
, A
VDD
2.3 2.5 2.7 V
C
LK_INT, CLK_INC, FB_INC
,
FB_INT
0.4 V
DD
/2 - 0.18 V
PD# -0.3 0.7 V
C
LK_INT, CLK_INC, FB_INC
,
FB_INT
V
DD
/2 + 0.18 2.1 V
PD# 1.7 V
DD
+ 0.6 V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DD
+ 0.3 V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36 V
DD
+ 0.6 V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.7 V
DD
+ 0.6 V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2 V
DD
/2 V
DD
/2 + 0.2 V
High level output current I
OH
-12 mA
Low level output current I
OL
12 mA
High Impedance
Output Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND 0.1 ±10 mA
Operating free-air
temperature
T
A
085°C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage V
IL
High level input voltage V
IH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal must be crossing.
5
ICS93V857-XXX
0693M—02/19/09
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency
3
freq
op
2.5V+0.2V
33 233 MHz
Application Frequency
Range
3
freq
App
2.5V+0.2V
60 170 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
100 µs
Switching Characteristics
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output 5.5 ns
High-to low level propagation
delay time
t
PHL
1
CLK_IN to any output 5.5 ns
Output enable time t
en
PD# to any output 5 ns
Output disable time t
dis
PD# to any output 5 ns
Period jitter t
jit (per)
66/100/125/133/167MHz -40 40 ps
100 to <170MHz -100 100 ps
≥
170MHz to 233MHz
-120
50
ps
Input clock slew rate t
sl(I)
14v/ns
Output clock slew rate t
sl(o)
66/100/133/167MHz 1 2 v/ns
Cycle to Cycle Jitter
1
t
cyc
-t
cyc
66/100/125/133/167MHz 60 ps
Phase error
t
(phase error)
4
-50 0 50 ps
Output to Output Skew t
skew
40 60 ps
Rise Time, Fall Time t
r
, t
f
Load = 120
Ω
/16pF 650 800 950 ps
t
jit(hper)
Half-period jitter
6
ICS93V857-XXX
0693M—02/19/09
GND
ICS93V857
V
DD
V
DD
/2
V
(CLKC)
V
(CLKC)
SCOPE
C=14pF
-VDD/2
-VDD/2
-VDD/2
VDD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V
(TT)
V
(TT)
C=14pF
NOTE: V
(TT)
=
GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS93V857
Figure 3. Cycle-to-Cycle Jitter
P1-P3P4-P6P7-P9P10-P11

93V857BG-025LFT

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Buy 93V857BG-025LFT
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IC CLK BUF DDR 233MHZ 1CIRC
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