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93V857BG-025LFT

P1-P3P4-P6P7-P9P10-P11
7
ICS93V857-XXX
0693M—02/19/09
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=
1
n=
N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t
(skew)
Y
#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y
X
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output
Skew
1
f
O
t
=
t
-
(jit_per)
t
c(n)
C(n)
1
f
O
Figure 6. Period Jitter
8
ICS93V857-XXX
0693M—02/19/09
Clock Inputs
and Outputs
80%
20%
80%
20%
t
slr
t
slf
V
ID
,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement
Information
t
jit(hper_n)
t
jit(hper_n+1)
1
f
o
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t
jit(hper)
t
jit(hper_n)
1
2xf
O
=-
9
ICS93V857-XXX
0693M—02/19/09
Ordering Information
93V857yG-025LFT 93V857yG-125LFT 93V857yG-130LFT
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Example:
XXXX y G - PPP LF T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil)
(0.020 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α
0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10 - 0 0 3 9
N
D mm. D (inch)
Ref erence Doc.: JEDEC Pub licat ion 95, M O-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Choice of static phase offset available, for easy board tuning;
-XXX = device pattern number for options listed below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
P1-P3P4-P6P7-P9P10-P11

93V857BG-025LFT

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Description:
IC CLK BUF DDR 233MHZ 1CIRC
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