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CAT9555WI-T1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 11
1 Publication Order Number:
CAT9555/D
CAT9555
16-bit I
2
C and SMBus I/O
Port with Interrupt
Description
The CAT9555 is a CMOS device that provides 16−bit parallel
input/output port expansion for I
2
C and SMBus compatible
applications. These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9555 consists of two 8−bit Configuration ports (input or
output), Input, Output and Polarity inversion registers, and an
I
2
C/SMBus−compatible serial interface.
Any of the sixteen I/Os can be configured as an input or output by
writing to the configuration register. The system master can invert the
CAT9555 input data by writing to the active−high polarity inversion
register.
The CAT9555 features an active low interrupt output which
indicates to the system master that an input state has changed.
The three address input pins provide the device’s extended
addressing capability and allow up to eight devices to share the same
bus. The fixed part of the I
2
C slave address is the same as the
CAT9554, allowing up to eight of these devices in any combination to
be connected on the same bus.
Features
• 400 kHz I
2
C Bus Compatible
• 2.3 V to 5.5 V Operation
• Low Stand−by Current
• 5 V Tolerant I/Os
• 16 I/O Pins that Default to Inputs at Power−up
• High Drive Capability
• Individual I/O Configuration
• Polarity Inversion Register
• Active Low Interrupt Output
• Internal Power−on Reset
• No Glitch on Power−up
• Noise Filter on SDA/SCL Inputs
• Cascadable up to 8 Devices
• Industrial Temperature Range
• 24−lead SOIC and TSSOP, and 24−pad TQFN (4 x 4 mm) Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• White Goods (dishwashers, washing machines)
• Handheld Devices (cell phones, PDAs, digital cameras)
• Data Communications (routers, hubs and servers)
http://onsemi.com
SOIC−24
W SUFFIX
CASE 751BK
TSSOP−24
Y SUFFIX
CASE 948AR
TQFN−24
HV6 SUFFIX
CASE 510AG
MARKING DIAGRAMS
TQFN−24
HT6 SUFFIX
CASE 510AN
A3B
CAT9555WI
YMXXXX
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
3 = Matte−Tin Lead Finish
B = Product Revision (Fixed as “B”)
CAT955W = Device Code (SOIC)
CAT9555Y = Device Code (TSSOP)
I = Industrial Temperature Range
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
XXXX = Last Four Digits of Assembly Lot Number
HHHH = Device Code MAAB = HT6
LAAB = HV6
A = Assembly Location
XXX = Last Three Digits of Assembly Lot Number
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
CC = Country Code TH = Thailand
MY = Malaysia
HHHH
AXXX
YMCC
AB
CAT9555YI
3YMXXX
(TQFN)
(SOIC)
(TSSOP)
CAT9555
http://onsemi.com
2
Figure 1. Pin Configurations
A0
I/O
1.7
I/O
1.6
I/O
1.5
I/O
1.4
I/O
1.3
I/O
0.0
I/O
0.1
I/O
0.2
I/O
0.3
I/O
0.4
I/O
0.5
A2
A1
INT
V
CC
SDA
SCL
I/O
0.6
I/O
0.7
V
SS
I/O
1.0
I/O
1.1
I/O
1.2
SOIC (W), TSSOP (Y)
(Top View)
TQFN (HV6, HT6)
(Top View)
A0
I/O
1.7
I/O
1.6
I/O
1.5
I/O
1.4
I/O
1.3
I/O
1.2
I/O
1.1
I/O
1.0
SCL
SDA
V
CC
1
I/O
0.7
V
SS
I/O
0.5
I/O
0.6
I/O
0.3
I/O
0.4
I/O
0.1
I/O
0.2
A2
I/O
0.0
INT
A1
1
Figure 2. Block Diagram
8−BIT
WRITE pulse
READ pulse
LP FILTER
POWER−ON
RESET
INPUT
FILTER
CONTROL
A0
A1
A2
SDA
SCL
8−BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
V
CC
V
SS
I
2
C/SMBUS
INT
V
INT
INPUT/
OUTPUT
PORTS
I/O
1.0
I/O
1.1
I/O
1.2
I/O
1.3
I/O
1.4
I/O
1.5
I/O
1.6
I/O
1.7
I/O
0.0
I/O
0.1
I/O
0.2
I/O
0.3
I/O
0.4
I/O
0.5
I/O
0.6
I/O
0.7
Note: All I/Os are set to inputs at RESET.
CAT9555
http://onsemi.com
3
Table 1. PIN DESCRIPTION
SOIC / TSSOP TQFN Pin Name Function
1 22 INT Interrupt Output (open drain)
2 23 A1 Address Input 1
3 24 A2 Address Input 2
4−11 1−8 I/O
0.0
− I/O
0.7
I/O Port 0.0 to I/O Port 0.7
12 9 V
SS
Ground
13−20 10−17 I/O
1.0
− I/O
1.7
I/O Port 1.0 to I/O Port 1.7
21 18 A0 Address Input 0
22 19 SCL Serial Clock
23 20 SDA Serial Data
24 21 V
CC
Power Supply
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
V
CC
with Respect to Ground −0.5 to +6.5 V
Voltage on Any Pin with Respect to Ground −0.5 to +5.5 V
DC Current on I/O
1.0
to I/O
1.7
, I/O
0.0
to I/O
0.7
±50 mA
DC Input Current ±20 mA
V
CC
Supply Current 160 mA
V
SS
Supply Current 200 mA
Package Power Dissipation Capability (T
A
= 25°C) 1.0 W
Junction Temperature +150 °C
Storage Temperature −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Units
V
ZAP
(Note 1) ESD Susceptibility JEDEC Standard JESD 22 2000 V
I
LTH
(Note 1) Latch−up JEDEC JESD78A 100 mA
1. This parameter is tested initially and after a design or process change that affects the parameter.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

CAT9555WI-T1

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Manufacturer:
ON Semiconductor
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