CAT9555
http://onsemi.com
10
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O pins
defined as inputs. Reads from the output port register reflect
the value that is in the flip-flop controlling the output, not the
actual I/O pin value.
The polarity inversion register allows the user to invert the
polarity of the input port register data. If a bit in this register
is set (“1”) the corresponding input port data is inverted. If
a bit in the polarity inversion register is cleared (“0”), the
original input port polarity is retained.
The configuration register sets the directions of the ports.
Set the bit in the configuration register to enable the
corresponding port pin as an input with a high impedance
output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At power-up,
the I/Os are configured as inputs with a weak pull-up resistor
to V
CC
.
Writing to the Port Registers
Data is transmitted to the CAT9555 registers using the
write mode shown in Figure 10 and Figure 11.
The CAT9555 registers are configured to operate at four
register pairs: Input Ports, Output Ports, Polarity Inversion
Ports and Configuration Ports. After sending data to one
register, the next data byte will be sent to the other register
in the pair. For example, if the first byte of data is sent to the
Configuration Port 1 (register 7), the next byte will be stored
in the Configuration Port 0 (register 6). Each 8-bit register
may be updated independently of the other registers.
Reading the Port Registers
The CAT9555 registers are read according to the timing
diagrams shown in Figure 12 and Figure 13. Data from the
register, defined by the command byte, will be sent serially
on the SDA line. Data is clocked into the register on the
failing edge of the acknowledge clock pulse. After the first
byte is read, additional data bytes may be read, but the
second read will reflect the data from the other register in the
pair. For example, if the first read is data from Input Port 0,
the next read data will be from Input Port 1. The transfer is
stopped when the master will not acknowledge the data byte
received and issue the STOP condition.
Figure 10. Write to Output Port Register
12
SCL
WRITE TO PORT
DATA OUT FROM PORT 0
345678
SDA
A
slave address
data to port 0
start condition
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
9
command byte
DATA 11.7
1.0
A
S 0 1 0 0 A2 A1 A0 0
DATA VALID
P
A
A0000000
DATA 0
1
0.7
0.0
stop
condition
DATA OUT FROM PORT 1
t
pv
t
pv
data to port 1
R/W
12
SCL
345678
SDA
AA A
DATA 0
slave address data to configuration 0
start condition
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
9
00000011
command byte
MSB
LSB
DATA 1
MSB LSB
A
S 0 1 0 0 A2 A1 A0 0
12345678912345678912345
P
A
Figure 11. Write to Configuration Register
R/W
data to configuration 1
