MAX1183ECM+D Datasheet MAX1183ECM+D, MAX1183ECM+TD | P10-P12

MAX1183

Detailed Description

The MAX1183 uses a nine-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half-clock cycle.

Including the delay through the output latch, the total

clock-cycle latency is five clock cycles.

One-and-a-half bit (2-comparator) flash ADCs convert

the held-input voltages into a digital code. The digital-

to-analog converters (DACs) convert the digitized

results back into analog voltages, which are then sub-

tracted from the original held-input signals. The resulting

error signals are then multiplied by two, and the residues

are passed along to the next pipeline stages where the

process is repeated until the signals have been

processed by all nine stages. Digital error correction

compensates for ADC comparator offsets in each of

these pipeline stages and ensures no missing codes.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

10 ______________________________________________________________________________________

T/H

OUT

FLASH

ADC

DAC

1.5 BITS

INA

STAGE 1 STAGE 2

D9A–D0A

INA

= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

INB

= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

DIGITAL CORRECTION LOGIC

STAGE 8

STAGE 9

2-BIT FLASH

ADC

T/H

OUT

FLASH

ADC

DAC

1.5 BITS

INB

STAGE 1 STAGE 2

D9B–D0B

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASH

ADC

T/H

Figure 1. Pipelined Architecture—Stage Blocks

Pin Description (continued)

PIN NAME FUNCTION

41 D6A Three-State Digital Output, Bit 6, Channel A

42 D7A Three-State Digital Output, Bit 7, Channel A

43 D8A Three-State Digital Output, Bit 8, Channel A

44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A

45 REFOUT

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor

divider.

46 REFIN Reference Input. V

REFIN

= 2 x (V

REFP

- V

REFN

). Bypass to GND with a >1nF capacitor.

47 REFP

Positive Reference Input/Output. Conversion range is ± (V

REFP

- V

REFN

Bypass to GND with a > 0.1µF capacitor.

48 REFN

Negative Reference Input/Output. Conversion range is ± (V

REFP

- V

REFN

Bypass to GND with a > 0.1µF capacitor.

— EP Exposed Pad. Connect to analog ground.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the

input track-and-hold (T/H) circuits in both track-and-hold

mode. In track mode, switches S1, S2a, S2b, S4a, S4b,

S5a, and S5b are closed. The fully differential circuits

sample the input signals onto the two capacitors (C2a

and C2b) through switches S4a and S4b. S2a and S2b

set the common mode for the amplifier input, and open

simultaneously with S1, sampling the input waveform.

Switches S4a and S4b are then opened before switch-

es S3a and S3b connect capacitors C1a and C1b to

the output of the amplifier and switch S4c is closed.

The resulting differential voltages are held on capaci-

tors C2a and C2b. The amplifiers are used to charge

capacitors C1a and C1b to the same values originally

held on C2a and C2b. These values are then presented

to the first-stage quantizers and isolate the pipelines

from the fast-changing inputs. The wide input bandwidth

T/H amplifiers allow the MAX1183 to track-and-sam-

ple/hold analog inputs of high frequencies (> Nyquist).

The ADC inputs (INA+, INB+, INA- and INB-) can be

driven either differentially or single-ended. Match the

impedance of INA+ and INA-, as well as INB+ and INB-

and set the common-mode voltage to midsupply

/2) for optimum performance.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1183 is determined by

the internally generated voltage difference between

REFP (V

/2 + V

REFIN

/4) and REFN (V

/2 -

REFIN

/4). The full-scale range for both on-chip ADCs is

adjustable through the REFIN pin, which is provided for

this purpose. REFOUT, REFP, COM (V

/2), and REFN

are internally buffered low-impedance outputs.

The MAX1183 provides three modes of reference

operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal refer-

ence output REFOUT to REFIN through a resistor (e.g.,

10kΩ) or resistor divider, if an application requires a

reduced full-scale range. For stability and noise filtering

purposes, bypass REFIN with a >10nF capacitor to

GND. In internal reference mode, REFOUT, COM, REFP,

and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference

voltage levels externally by applying a stable and accu-

rate voltage at REFIN. In this mode, COM, REFP, and

REFN become outputs. REFOUT may be left open or

connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN

to GND. This deactivates the on-chip reference buffers

for REFP, COM, and REFN. With their buffers shut

down, these nodes become high impedance and may

be driven through separate external reference sources.

Clock Input (CLK)

The MAX1183’s CLK input accepts CMOS-compatible

clock signals. Since the interstage conversion of the

device depends on the repeatability of the rising and

falling edges of the external clock, use a clock with low

jitter and fast rise and fall times (< 2ns). In particular,

sampling occurs on the rising edge of the clock signal,

requiring this edge to provide lowest possible jitter. Any

significant aperture jitter would limit the SNR perfor-

mance of the on-chip ADCs as follows:

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 11

S3b

S3a

COM

S5b

S5a

INB+

INB-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

HOLD

CLK

INTERNAL

NONOVERLAPPING

CLOCK SIGNALS

TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

INA+

INA-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

S2a

S2b

MAX1183

Figure 2. MAX1183 T/H Amplifiers

SNR

IN AJ

log =×

×× ×

⎛

⎝

⎜

⎞

⎠

⎟

2 π

MAX1183

where f

represents the analog input frequency and

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling

applications. The clock input should always be consid-

ered as an analog input and routed away from any ana-

log input or other digital signal lines.

The MAX1183 clock input operates with a voltage thresh-

old set to V

/2. Clock inputs with a duty cycle other

than 50% must meet the specifications for high and low

periods as stated in the Electrical Characteristics.

System Timing Requirements

Figure 3 depicts the relationship between the clock

input, analog input, and data output. The MAX1183

samples at the rising edge of the input clock. Output

data for channels A and B is valid on the next rising

edge of the input clock. The output data has an internal

latency of five clock cycles. Figure 4 also determines

the relationship between the input clock parameters

and the valid output data on channels A and B.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

)

All digital outputs, D0A–D9A (Channel A) and D0B–D9B

(Channel B) are TTL/CMOS logic-compatible. There is a

five-clock-cycle latency between any particular sample

and its corresponding output data. The output coding

can be chosen to be either straight offset binary or

two’s complement (Table 1) controlled by a single pin

(T/B). Pull T/B low to select offset binary and high to

activate two’s complement output coding. The capaci-

tive load on the digital outputs D0A–D9A and D0B–D9B

should be kept as low as possible (<15pF) to avoid

large digital currents that could feed back into the ana-

log portion of the MAX1183, thereby degrading its

dynamic performance. Using buffers on the digital out-

puts of the ADCs can further isolate the digital outputs

from heavy capacitive loads. To further improve the

dynamic performance of the MAX1183, small-series

resistors (e.g., 100Ω) may be added to the digital out-

put paths close to the MAX1183.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

12 ______________________________________________________________________________________

N - 6

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N + 6

N + 1

5-CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

D9A–D0A

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1

DATA OUTPUT

D9B–D0B

Figure 3. System Timing Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1183ECM+D

Mfr. #:

Buy MAX1183ECM+D

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 10-Bit 2Ch 40Msps High Speed ADC

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MAX1183ECM+D

MAX1183ECM+D

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