Figure 4 displays the timing relationship between output
enable and data output valid, as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1183 offers two power-save modes—sleep and
full power-down modes. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to 2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
DD
/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed op amps follows the amplifiers. The
user may select the R
ISO
and C
IN
values to optimize
the filter performance, to suit a particular application.
For the application in Figure 5, a R
ISO
of 50 is placed
before the capacitive load to prevent ringing and
oscillation. The 22pF C
IN
capacitor acts as a small
bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully dif-
ferential signal, required by the MAX1183 for optimum
performance. Connecting the center tap of the trans-
former to COM provides a V
DD
/2 DC level shift to the
input. Although a 1:1 transformer is shown, a step-up
transformer may be selected to reduce the drive require-
ments. A reduced signal swing from the input driver, such
as an op amp, may also improve the overall distortion.
In general, the MAX1183 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
Typical QAM Demodulation Application
The most frequently used modulation technique for dig-
ital communications applications is probably the quad-
rature amplitude modulation (QAM). Typically found in
spread-spectrum-based systems, a QAM signal repre-
sents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the base-
band signal with quadrature outputs, a local oscillator
followed by subsequent up-conversion can generate
the QAM signal. The result is an in-phase (I) and
a quadrature (Q) carrier component, where the Q
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 13
OUTPUT
D9A–D0A
OE
t
DISABLE
t
ENABLE
HIGH-ZHIGH-Z
VALID DATA
OUTPUT
D9B–D0B
HIGH-ZHIGH-Z
VALID DATA
Figure 4. Output Timing Diagram
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
T/B = 0
TWO'S COMPLEMENT
T/B = 1
V
REF
x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111
V
REF
x 1/512 + 1LSB 10 0000 0001 00 0000 0001
0 Bipolar Zero 10 0000 0000 00 0000 0000
- V
REF
x 1/512 - 1LSB 01 1111 1111 11 1111 1111
-V
REF
x 512/512 -FULL SCALE +1LSB 00 0000 0001 10 0000 0001
-V
REF
x 512/512 -FULL SCALE 00 0000 0000 10 0000 0000
Table 1. MAX1183 Output Codes for Differential Inputs
*V
REF
= V
REFP
- V
REFN
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
14 ______________________________________________________________________________________
INPUT
300
-5V
+5V
0.1µF
0.1µF
0.1µF
-5V
600
300
300
INA+
INA-
LOWPASS FILTER
COM
600
+5V
-5V
0.1µF
600
300
600
300
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300
MAX4108
MAX1183
INB+
INB-
MAX4108
MAX4108
LOWPASS FILTER
INPUT
300
-5V
+5V
0.1µF
0.1µF
0.1µF
C
IN
22pF
-5V
600
300
300
LOWPASS FILTER
600
+5V
-5V
0.1µF
600
300
600
300
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300
MAX4108
MAX4108
MAX4108
300
LOWPASS FILTER
R
IS0
50
C
IN
22pF
R
IS0
50
C
IN
22pF
R
IS0
50
C
IN
22pF
R
IS0
50
Figure 5. Typical Application for Single-Ended to Differential Conversion
component is 90 degree phase-shifted with respect to
the in-phase component. At the receiver, the QAM signal
is divided down into its I and Q components, essentially
representing the modulation process reversed. Figure 8
displays the demodulation process performed in the
analog domain, using the dual matched 3V, 10-bit ADC
(MAX1183), and the MAX2451 quadrature demodulator
to recover and digitize the I and Q baseband signals.
Before being digitized by the MAX1183, the mixed-down
signal components may be filtered by matched analog
filters, such as Nyquist or pulse-shaping filters, which
remove any unwanted images from the mixing process,
thereby enhancing the overall signal-to-noise (SNR) per-
formance and minimizing intersymbol interference.
Grounding, Bypassing, and
Board Layout
The MAX1183 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V
DD
, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV
DD
) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 15
MAX1183
T1
N.C.
V
IN
6
1
5
2
43
22pF
22pF
0.1µF
0.1µF
2.2µF
25
25
MINICIRCUITS
TT1–6
T1
N.C.
V
IN
6
1
5
2
4
3
22pF
22pF
0.1µF
0.1µF
2.2µF
25
25
MINICIRCUITS
TT1–6
INA-
INA+
INB-
INB+
COM
Figure 6. Transformer-Coupled Input Drive
MAX1183
0.1µF
1k
1k
100
100
C
IN
22pF
C
IN
22pF
INB+
INB-
COM
INA+
INA-
0.1µF
R
ISO
50
R
ISO
50
REFP
REFN
V
IN
MAX4108
0.1µF
1k
1k
100
100
C
IN
22pF
C
IN
22pF
0.1µF
R
ISO
50
R
ISO
50
REFP
REFN
V
IN
MAX4108
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive

MAX1183ECM+D

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 40Msps High Speed ADC
Lifecycle:
New from this manufacturer.
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