LTC3621HMS8E-23.3#TRPBF

LTC3621/LTC3621-2
13
3621fc
For more information www.linear.com/LTC3621
applicaTions inForMaTion
2. The switching current is the sum of the MOSFET driver
and control currents. The power MOSFET driver current
results from switching the gate capacitance of the power
MOSFETs. Each time a power MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from V
IN
to ground. The resulting dQ/dt is a
current out of V
IN
that is typically much larger than the
DC control bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of
the internal top and bottom power MOSFETs and f is
the switching frequency. The power loss is thus:
Switching Loss = I
GATECHG
• V
IN
The gate charge loss is proportional to V
IN
and f and
thus their effects will be more pronounced at higher
supply voltages and higher frequencies.
3. Other “hidden” losses such as transition loss and cop
-
per trace and internal load resistances can account for
additional efficiency
degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3621 internal power devices
switch quickly enough that these losses are not sig
-
nificant compared to other sources. These losses plus
other losses, including diode conduction losses during
dead-time
and
inductor core losses, generally account
for less than 2% total additional loss.
Thermal Conditions
In a majority of applications, the LTC3621 does not dis
-
sipate much heat due to its high efficiency and low thermal
resistance of its exposed pad package. However, in ap-
plications where the LTC3621 is running at high ambient
temperature, high V
IN
, high switching frequency, and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
both power switches will be turned off until the temperature
drops about 15°C cooler.
To avoid the LTC3621 from exceeding the maximum junc
-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
θ
JA
As an example, consider the case when the LTC3621
is used in applications where V
IN
= 12V, I
OUT
= 1A,
f = 2.25MHz, V
OUT
= 1.8V. The equivalent power MOSFET
resistance R
SW
is:
R
SW
=R
DS(ON)TOP
V
OUT
V
IN
+R
DS(ON)BOT
1–
V
OUT
V
IN
= 370mΩ
1.8V
12V
+150mΩ 1–
1.8V
12V
=183m
The V
IN
current during 2.25MHz force continuous opera-
tion with no load is about 5mA, which includes switching
and internal biasing current loss, transition loss, inductor
core loss and other losses in the application. Therefore,
the total power dissipated by the part is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• I
IN(Q)
= 1A
2
• 183mΩ + 12V • 5mA
= 243mW
The DFN 2mm × 3mm package junction-to-ambient thermal
resistance, θ
JA
, is around 64°C/W. Therefore, the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
T
J
= 0.243W • 64°C/W + 25°C = 40.6°C
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 25°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. Redoing the calculation
assuming that R
SW
increased 5% at 40.6°C yields a new
junction temperature of 41.1°C. If the application calls
for a higher ambient temperature and/or higher switching
frequency, care should be taken to reduce the temperature
rise of the part by using a heat sink or forced air flow.
LTC3621/LTC3621-2
14
3621fc
For more information www.linear.com/LTC3621
V
OUT
C
OUT
L1
3621 F03
V
IN
C
IN
GND
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3621 (refer to Figure 3). Check the following in
your layout:
5. Keep sensitive components away from the SW pin. The
feedback resistors and INTV
CC
bypass capacitors should
be routed away from the SW trace and the inductor.
6. A ground plane is preferred.
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
Design Example
As a design example, consider using the LTC3621 in an
application with the following specifications:
V
IN
= 10.8V to 13.2V
V
OUT
= 3.3V
I
OUT(MAX)
= 1A
I
OUT(MIN)
= 0A
f
SW
= 2.25MHz
Because efficiency and quiescent current is important at
both 500mA and 0A current states, Burst Mode operation
will be utilized.
Given the internal oscillator of 2.25MHz, we can calcu
-
late the inductor value for about 40% ripple current at
maximum V
IN
:
L =
3.3V
2.25MHz 0.4A
1–
3.3V
13.2V
= 2.75µH
Given this, a 2.7µH or 3.3µH, >1.2A inductor would suffice.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22µF ceramic capacitor will be used.
C
IN
should be sized for a maximum current rating of:
I
RMS
=1A
3.3V
13.2V
13.2V
3.3V
1
1/2
= 0.43A
Decoupling the V
IN
pin with 10µF ceramic capacitors is
adequate for most applications.
applicaTions inForMaTion
1. Do the capacitors C
IN
connect to the V
IN
pin and GND
pin as close as possible? These capacitors provide the
AC current to the internal power MOSFETs and their
drivers.
2. Are C
OUT
and L closely connected? The (–) plate of
C
OUT
returns current to GND.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line ter-
minated near GND. The feedback signal V
FB
should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
4. Solder the exposed pad (Pin 7 for DFN, Pin 9 for MSOP)
on the bottom of the package to the GND plane. Connect
this GND plane to other layers with thermal vias to help
dissipate heat from the LTC3621.
Figure 3. Sample PCB Layout
LTC3621/LTC3621-2
15
3621fc
For more information www.linear.com/LTC3621
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
×
45° CHAMFER
0.25 ±0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3621HMS8E-23.3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 17V, 1A, 1MHz Synchronous Step-Down Regulator with Ultralow Quiescent Current
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union