2SC0650P2Ax-17
Preliminary Data Sheet
IGBT-Driver.com Page 5
7) Output rise and fall times are measured between 10% and 90% of the nominal output swing with an
output load of 4.7Ω and 270nF. The values are given for the driver side of the gate resistors. The time
constant of the output load in conjunction with the present gate resistors leads to an additional delay
at the load side of the gate resistors.
8) External blocking capacitors are to be placed between VISOx and VEx as well as VEx and COMx for
gate charges exceeding 3µC. Ceramic capacitors are recommended. A minimum external blocking
capacitance of 3µF is recommended for every 1µC of gate charge beyond 3µC. Insufficient external
blocking can lead to reduced driver efficiency and thus to thermal overload.
9) The minimum response time given is valid for the circuit given in the description and application
manual (Fig. 6) with the values of table 1 (C
ax
=0pF, R
thx
=43kΩ).
10) The blocking time sets a minimum time span between the end of any fault state and the start of
normal operation (remove fault from pin SOx). The value of the blocking time can be adjusted at pin
TB. The specified blocking time is valid if TB is connected to GND.
11) This specification guarantees that the drive information will be transferred reliably even at a high DC-
link voltage and with ultra-fast switching operations.
12) Undervoltage monitoring of the primary-side supply voltage (VCC to GND). If the voltage drops below
this limit, a fault is transmitted to both SOx outputs and the power semiconductors are switched off.
13) Undervoltage monitoring of the secondary-side supply voltage (VISOx to VEx and VEx to COMx which
correspond with the approximate turn-on and turn-off gate-emitter voltages). If the corresponding
voltage drops below this limit, the IGBT is switched off and a fault is transmitted to the corresponding
SOx output.
14) Transmission delay of fault state from the secondary side to the corresponding primary status output.
15) HiPot testing (= dielectric testing) must generally be restricted to suitable components. This gate
driver is suited for HiPot testing. Nevertheless, it is strongly recommended to limit the testing time to
1s slots as stipulated by EN 50178. Excessive HiPot testing at voltages much higher than 1200V
AC(eff)
may lead to insulation degradation. No degradation has been observed over 1min. testing at
5000V
AC(eff)
. Every production sample shipped to customers has undergone 100% testing at the given
value for 1s.
16) Partial discharge measurement is performed in accordance with IEC 60270 and isolation coordination
specified in EN 50178. The partial discharge extinction voltage between primary and either secondary
side is coordinated for safe isolation to EN 50178. The minimum value given is designed to include
appropriate safety margins for long-term ageing. Accelerated ageing tests show virtually no insulation
deterioration. Minimum partial discharge extinction voltages remain >2100V even after 2600 slow
thermal cycles between –40°C and 125°C and also after 500 thermal shock cycles between –55°C and
150°C.
17) Jitter measurements are performed with input signals INx switching between 0V and 5V referred to
GND, with a corresponding rise time and fall time of 15ns.
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This data sheet specifies devices but cannot promise to deliver any specific characteristics. No warranty or
guarantee is given – either expressly or implicitly – regarding delivery, performance or suitability.
CT-Concept Technologie AG reserves the right to make modifications to its technical data and product
specifications at any time without prior notice. The general terms and conditions of delivery of CT-Concept
Technologie AG apply.
