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4
Table 5. A.C. CHARACTERISTICS (V
CC
= 2.3 V to 5.5 V; T
A
= 40°C to +85°C, unless otherwise specified.) (Note 8)
Symbol
Parameter
Standard I
2
C Fast I
2
C
Units
Min Max Min Max
F
SCL
Clock Frequency 100 400 kHz
t
HD:STA
START Condition Hold Time 4 0.6
ms
t
LOW
Low Period of SCL Clock 4.7 1.3
ms
t
HIGH
High Period of SCL Clock 4 0.6
ms
t
SU:STA
START Condition Setup Time 4.7 0.6
ms
t
HD:DAT
Data In Hold Time 0 0
ms
t
SU:DAT
Data In Setup Time 250 100 ns
t
R
(Note 9) SDA and SCL Rise Time 1000 300 ns
t
F
(Note 9) SDA and SCL Fall Time 300 300 ns
t
SU:STO
STOP Condition Setup Time 4 0.6
ms
t
BUF
(Note 9) Bus Free Time Between STOP and START 4.7 1.3
ms
t
AA
SCL Low to Data Out Valid 3.5 0.9
ms
t
DH
Data Out Hold Time 100 50 ns
T
i
(Note 9) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
Symbol Parameter Min Max Units
PORT TIMING
t
PV
Output Data Valid 200 ns
t
PS
Input Data Setup Time 100 ns
t
PH
Input Data Hold Time 1
ms
INTERRUPT TIMING
t
IV
Interrupt Valid 4
ms
t
IR
Interrupt Reset 4
ms
8. Test conditions according to “AC Test Conditions” table.
9. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall time 10 ns
CMOS Input Voltages 0.2 V
CC
to 0.8 V
CC
CMOS Input Reference Voltages 0.3 V
CC
to 0.7 V
CC
TTL Input Voltages 0.4 V to 2.4 V
TTL Input Reference Voltages 0.8 V, 2.0 V
Output Reference Voltages 0.5 V
CC
Output Load: SDA, INT Current Source I
OL
= 3 mA; C
L
= 100 pF
Output Load: I/Os Current Source: I
OL
/I
OH
= 10 mA; C
L
= 50 pF
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5
SCL
SDA IN
SDA OUT
Figure 2. I
2
C Serial Interface Timing
t
SU:STA
t
AA
t
F
t
HD:STA
t
HD:DAT
t
LOW
t
DH
t
R
t
SU:DAT
t
LOW
t
HIGH
t
SU:STO
t
BUF
Pin Description
SCL: Serial Clock
The serial clock input clocks all data transferred into or out
of the device. The SCL line requires a pullup resistor if it
is driven by an open drain output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wireORed with other open drain or
open collector outputs. A pullup resistor must be connected
from SDA line to V
CC
. The value of the pullup resistor, R
P
,
can be calculated based on minimum and maximum values
from Figure 3 and Figure 4 (see Note).
A0, A1, A2: Device Address Inputs
These inputs are used for extended addressing capability.
The A0, A1, A2 pins should be hardwired to V
CC
or V
SS
.
When hardwired, up to eight CAT9554/9554As may be
addressed on a single bus system. The levels on these inputs
are compared with corresponding bits, A2, A1, A0, from the
slave address byte.
I/O
0
to I/O
7
: Input / Output Ports
Any of these pins may be configured as input or output.
The simplified schematic of I/O
0
to I/O
7
is shown in
Figure 5. When an I/O is configured as an input, the Q1 and
Q2 output transistors are off creating a high impedance input
with a weak pullup resistor (typical 100 kW). If the I/O pin
is configured as an output, the pushpull output stage is
enabled. Care should be taken if an external voltage is
applied to an I/O pin configured as an output due to the low
impedance paths that exist between the pin and either V
CC
or V
SS
.
Figure 3. Minimum R
P
Value vs.
Supply Voltage
Figure 4. Maximum R
P
Value vs.
Bus Capacitance
V
CC
(V) C
BUS
(pF)
4.84.44.03.63.22.82.42.0
0
0.5
1.0
1.5
2.0
2.5
400350300200150100500
0
1
2
3
4
6
7
8
R
Pmin
(KW)
R
Pmax
(KW)
5.2 5.6
I
OL
= 3 mA @ V
OLmax
250
5
Fast Mode I
2
C Bus /
tr max 300 ns
NOTE: According to the Fast Mode I
2
C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus
loads between 200 pF and 400 pF, the pullup device can be a current source (Imax = 3 mA) or a switched resistor circuit.
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6
INT: Interrupt Output
The opendrain interrupt output is activated when one of
the port pins configured as an input changes state (differs
from the corresponding input port register bit state). The
interrupt is deactivated when the input returns to its previous
state or the input port register is read. Changing an I/O from
an output to an input may cause a false interrupt if the state
of the pin does not match the contents of the input port
register.
Output Port
Register Data
Input Port
Register Data
Polarity
Register Data
Polarity
Inversion Register
Write
Polarity
Register
Data from
Shift Register
Read Pulse
Write Pulse
Write
Configuration
Data from
Shift Register
Data from
Shift Register
Configuration
Register
D
Q
FF
D
Q
FF
D
Q
LATCH
D
Q
FF
Q1
Q2
Output Port
Register
Input Port
Register
Figure 5. Simplified Schematic of I/O
0
to I/O
7
Pulse
Q
C
K
Q
C
K
C
K
Q
Q
C
K
To INT
V
SS
V
CC
I/O
0
to I/O
7
100 kW

CAT9554AWI-GT2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders I2C/SMBUS Expander 8B,w/Int
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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