Philips Semiconductors Product data
74F82710-bit buffer/line driver, non-inverting (3-State)
2
2004 Jan 21
FEATURES
• High impedance NPN base inputs for reduced loading (20 µA in
HIGH and LOW states)
• I
IL
is 20 µA vs FAST family spec of 600 µA
• Ideal where high speed, light bus loading and increased fan-in are
required
• Controlled rise and fall times to minimize ground bounce
• Glitch free power-up in 3-State
• Flow through pinout architecture for microprocessor oriented
applications
• Outputs sink 64 mA
• 74F827 is available in SSOP type II package
DESCRIPTION
The 74F827 10-Bit buffer provides high performance bus interface
buffering for wide data/address paths or buses carrying parity. The
device has NOR Output Enables (OE
0, OE1) for maximum control
flexibility.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F827 6.0ns 60 mA
ORDERING INFORMATION
COMMERCIAL RANGE: V
CC
= 5 V
±
10%; T
amb
= 0
°
C to +70
°
C
Type number
Package
Name Description Version
N74F827N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1
N74F827D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
N74F827DB SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH / LOW
D0-D9 Data inputs 1.0/0.033 20 µA / 20 µA
OE0-OE1 Output enable inputs (active-LOW) 1.0/0.033 20 µA / 20 µA
Q0-Q9 Data outputs 1200/106.7 24 mA / 64 mA
NOTES:
One (1.0) FAST Unit Load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION
SF00266
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
OE
0
D
0
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q6
Q8
Q9
OE
1
GND
