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GTL2007PW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
GTL2007_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 16 February 2007 4 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for TSSOP28
GTL2007PW
VREF V
CC
1AO 1BI
2AO 2BI
5A 7BO1
6A 7BO2
EN1 EN2
11BI 11BO
11A 5BI
9BI 6BI
3AO 3BI
4AO 4BI
10AI1 10BO1
10AI2 10BO2
GND 9AO
002aab209
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Table 3. Pin description
Symbol Pin Description
VREF 1 GTL reference voltage
1AO 2 data output (LVTTL)
2AO 3 data output (LVTTL)
5A 4 data input/output (LVTTL), open-drain
6A 5 data input/output (LVTTL), open-drain
EN1 6 enable input (LVTTL)
11BI 7 data input (GTL)
11A 8 data input/output (LVTTL), open-drain
9BI 9 data input (GTL)
3AO 10 data output (LVTTL)
4AO 11 data output (LVTTL)
10AI1 12 data input (LVTTL)
10AI2 13 data input (LVTTL)
GND 14 ground (0 V)
9AO 15 data output (LVTTL)
10BO2 16 data output (GTL)
10BO1 17 data output (GTL)
4BI 18 data input (GTL)
3BI 19 data input (GTL)
GTL2007_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 16 February 2007 5 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
7. Functional description
Refer to Figure 1 “Logic diagram of GTL2007”.
7.1 Function tables
[1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and
Table 6.
6BI 20 data input (GTL)
5BI 21 data input (GTL)
11BO 22 data output (GTL)
EN2 23 enable input (LVTTL)
7BO2 24 data output (GTL)
7BO1 25 data output (GTL)
2BI 26 data input (GTL)
1BI 27 data input (GTL)
V
CC
28 positive supply voltage
Table 3. Pin description
…continued
Symbol Pin Description
Table 4. GTL input signals
H = HIGH voltage level; L = LOW voltage level.
Input Output
[1]
1BI/2BI/3BI/4BI/9BI 1AO/2AO/3AO/4AO/9AO
LL
HH
Table 5. EN1 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN1 1AO and 2AO 5A
L H 5BI disconnected
H follows BI 5BI connected
Table 6. EN2 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN2 3AO and 4AO 6A
L H 6BI disconnected
H follows BI 6BI connected
GTL2007_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 16 February 2007 6 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the
7BO1/7BO2 outputs.
[2] Open-drain input/output terminal is driven to logic LOW state by other driver.
[1] Open-drain input/output terminal is driven to logic LOW state by other driver.
Table 7. SMI signals
H = HIGH voltage level; L = LOW voltage level.
Input Input Output
10AI1/10AI2 9BI 10BO1/10BO2
LLL
LHL
HLL
HHH
Table 8. PROCHOT signals
H = HIGH voltage level; L = LOW voltage level.
Input Input/output Output
5BI/6BI 5A/6A (open-drain) 7BO1/7BO2
LLH
[1]
HL
[2]
L
HHH
Table 9. NMI signals
H = HIGH voltage level; L = LOW voltage level.
Input Input/output Output
11BI 11A (open-drain) 11BO
LHL
LL
[1]
H
HLH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

GTL2007PW,112

Mfr. #:
Buy GTL2007PW,112
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels 12-BIT XEON GTL TO
Lifecycle:
New from this manufacturer.
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