REVISION B 8/25/15
873991-147 DATA SHEET
8 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR
TABLE 6. AC CHARACTERISTICS, V
CC
= V
CCO
= 3.3V ± 5%, TA = 0°C TO 50°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency
QA, QB, QC 480 MHz
QD SYNC_SEL = 1 400 MHz
QD; NOTE 1 SYNC_SEL = 0 200 MHz
t(Ø)
Static Phase Offset; NOTE
2, 3
CLK, nCLK 170 325 ps
tsk(o) Output Skew; NOTE 4, 5 250 ps
tsk(w) Multiple Frequency Skew; NOTE 5, 6 350 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5
VCO_SEL = 0 50 ps
VCO_SEL = 1 55 ps
tjit(hcyc) Half-Cycle Jitter
NOTE 7 VCO_SEL = 0 375 ps
NOTE 8 VCO_SEL = 1 130 ps
f
VCO
PLL VCO Lock Range; NOTE 9
VCO_SEL = 0 400 960 MHz
VCO_SEL = 1 200 480 MHz
t
LOCK
PLL Lock Time 10 ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 0.2 1 ns
odc Output Duty Cycle
NOTE 7 VCO_SEL = 0 40 60 %
NOTE 8 VCO_SEL = 1 45 55 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is es-
tablished when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The
device will meet specifi cations after thermal equilibrium has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency.
NOTE 2: Defi ned as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Static phase offset is specifi ed for an input frequency of 50MHz with feedback in ÷8.
NOTE 4: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 6: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
CCO
/2.
NOTE 7: This value is based on the VCO frequency = 960MHz, output divider = 2.
NOTE 8: This value is based on the VCO frequency = 480MHz, output divider = 2.
NOTE 9: When VCO_SEL = 0, the PLL will be unstable with feedback confi gurations of ÷2, ÷4, ÷32 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback confi guration of ÷2.
