DS2436
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NOTES:
1. Temperature conversion takes up to 10 ms.
2. A/D conversion takes up to 10 ms.
3. Temperature and A/D conversions cannot take place simultaneously.
I/O SIGNALING
The DS2436 requires strict protocols to insure data integrity. The protocol consists of several types of
signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals,
with the exception of the presence pulse, are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2436 is shown in Figure 8.
A reset pulse followed by a presence pulse indicates the DS2436 is ready to send or receive data given the
correct ROM command and memory function command.
The bus master transmits (TX) a reset pulse (a low signal for a minimum of 480 μs). The bus master then
releases the line and goes into a receive mode (RX). The 1-Wire bus is pulled to a high state via the 5k
pullup resistor. After detecting the rising edge on the I/O pin, the DS2436 waits 15-60 μs and then
transmits the presence pulse (a low signal for 60-240 μs).
READ/WRITE TIME SLOTS
DS2436 data is read and written through the use of time slots to manipulate bits and a command word to
specify the transaction.
Write Time Slots
A write time slot is initiated when the host pulls the data line from a high logic level to a low logic level.
There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots
must be a minimum of 60 μs in duration with a minimum of a 1 μs recovery time between individual
write cycles.
The DS2436 samples the I/O line in a window from 15 μs to 60 μs after the I/O line falls. If the line is
high, a Write 1 occurs. If the line is low, a Write 0 occurs (see Figure 9).
For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then
released, allowing the data line to pull up to a high level within 15 μs after the start of the write time slot.
For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain
low for the duration of the write time slot.
