LTC4274A/LTC4274C
10
4274acfd
For more information www.linear.com/LTC4274A
TEST TIMING DIAGRAMS
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes
Figure 2. Current Limit Timing
Figure 3. DC Disconnect Timing
V
PORT
INT
V
OC
V
EE
t
DET
t
ME
t
MEL
V
MARK
V
CLASS
15.5V
20.5V
t
CLE
t
CLE
t
CLEON
PD
CONNECTED
0V
4274AC F01
FORCED-CURRENT
CLASSIFICATION
t
PON
FORCED-
VOLTAGE
V
LIM
V
CUT
0V
V
SENSE
TO V
EE
INT
4274AC F02
t
START
, t
ICUT
V
MIN
V
SENSE
TO V
EE
INT
t
DIS
t
MPS
4274AC F03
LTC4274A/LTC4274C
11
4274acfd
For more information www.linear.com/LTC4274A
TEST TIMING DIAGRAMS
Figure 4. Shut Down Delay Timing
Figure 5. I
2
C Interface Timing
V
GATE
V
EE
MSD
or
SHDN
t
SHDN
t
MSD
4274AC F04
SCL
SDA
t
1
t
2
t
3
t
r
t
f
t
5
t
6
t
7
t
8
t
4
4274AC F05
LTC4274A/LTC4274C
12
4274acfd
For more information www.linear.com/LTC4274A
I
2
C TIMING DIAGRAMS
Figure 6. Writing to a Register
Figure 7. Reading from a Register
SCL
SDA
4274AC F06
0 01
AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
STOP BY
MASTER
SCL
SDA
0 01
AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W
ACK
ACK
0 01
AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
ACK
ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
4274AC F07
STOP BY
MASTER
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE

LTC4274AIUHF-4#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN LTPoE++ 90W Single Powered Ethernet PSE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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