ZL40217 Data Sheet
4
Microsemi Corporation
1.0 Package Description
The device is packaged in a 32 pin QFN
26
28
30
32
12
10
8
64
2
NC
out5_p
out4_n
out5_n
NC
gnd
clk_p
VDD_core
out1_n
NC
out0_n
out1_p
gnd
out3_n
vdd
gnd
out2_p
14
16
18
2224 20
vdd
NC
out0_p
NC
clk_n
out2_n
gnd
out3_p
vdd
ctrl
NC
VDD_core
out4_p
vdd
vt
gnd (E-pad)
vt
Figure 2 - Pin Connections
ZL40217 Data Sheet
5
Microsemi Corporation
2.0 Pin Description
Pin # Name Description
3, 6 clk_p, clk_n, Differential Input (Analog Input). Differential (or single ended) input signals.
For all input configurations see “Clock Inputs” on page 6
28, 27,
26, 25,
24, 23,
18, 17,
16, 15,
14, 13
out0_p, out0_n
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
Differential Output (Analog Output). Differential outputs.
9, 19,
22, 32
vdd Positive Supply Voltage. 2.5 V
DC
or 3.3 V
DC
nominal.
1, 8 vdd_core Positive Supply Voltage. 2.5 V
DC
or 3.3 V
DC
nominal.
2, 7,
20, 21
gnd Ground. 0 V.
4vtOn-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
The use of this pin is detailed in section 3.1, “Clock Inputs“, for various input signal types.
5ctrlDigital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
This pin are internally pulled down to GND. The use of this pin is detailed in section 3.1,
“Clock Inputs“, for various input signal types.
10, 11,
12, 29,
30, 31
NC No Connection. Leave unconnected.
ZL40217 Data Sheet
6
Microsemi Corporation
3.0 Functional Description
he ZL40217 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to
750MHz.
The ZL40217 provides an internal input termination netwo
rk for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40217 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40217 is designed to fan out
low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simplified Diagram of input stage
This following figures give the components values and configu
ration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams were the ct
rl pin is "1" and the Vt pin is not connected, the Vt pin can be instead
connected to V
DD
with a capacitor. A capacitor can also help in Figure 4 between Vt and V
DD
. This capacitor will
minimize the noise at the point between the two inter
nal termination resistors and improve the overall performance
of the device.

ZL40217LDF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 1:6 LVDS Fanout Buffer w/Int. Term.
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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