LTC3113
13
3113f
APPLICATIONS INFORMATION
The choice of inductor style depends upon the price, sizing,
and EMI requirements of a particular application. Table 1
provides a small sampling of inductors that are well suited
to many LTC3113 buck-boost converter applications. All
inductor specifi cations are listed at an inductance value
of 2.2μH for comparison purposes but other values within
these inductor families are generally well suited to this
application. Within each family (i.e. at a fi xed size), the DC
resistance generally increases and the maximum current
generally decreases with increased inductance.
Table 1. Representative Buck-Boost Surface Mount Inductors
PART
NUMBER
VALUE
(μH)
DCR
(mΩ)
MAX DC
CURRENT (A)
SIZE (mm)
W × L × H
CoilCraft (www.coilcraft.com)
MSS1048 2.2 7.2 8.4
10 × 10.3 × 4
MSS1260 2.2 12 13.9
12.3 × 12.3 × 6
SER1052 2.2 4 10
10.6 × 10.6 × 5.2
Toko (www.toko.com)
D106C 2.4 7.7 10
10.3 × 10.3 × 6.7
FDA1055 2.2 4.8 10.5
11.6 × 10.8 × 5.5
FDA1254 2.2 4.5 14.7
13.5 × 12.6 × 5.4
Cooper (www.cooperbussmann.com)
HCP0703 2.2 18 14
7 × 7.3 × 3
HCP0704 2.3 16.5 11.5
6.8 × 6.8 × 4.2
HC8 2.6 11.4 10
10.9 × 10.4 × 4
TDK (www.component.tdk.com)
VLF100040 2.2 7.9 8.2
9.7 × 10 × 4
RLF12560 2.7 4.5 12
13 × 13 × 6
VLF12060 2.7 6.4 10
11.7 × 12 × 6
Wurth (www.we-online.com)
744066 2.2 10.5 6.8
10 × 10 × 3.8
744355 2 8 13
13.2 × 12.8 × 6.2
744324 2.4 4.8 17
10.5 × 10.2 × 4.7
OUTPUT CAPACITOR SELECTION
A low ESR output capacitor should be utilized at the buck-
boost converter output in order to minimize output voltage
ripple. Multilayer ceramic capacitors are an excellent choice
as they have low ESR and are available in small footprints.
The capacitor should be chosen large enough to reduce the
output voltage ripple to acceptable levels. Neglecting the
capacitor ESR and ESL, the peak-to-peak output voltage
ripple can be calculated by the following formulas, where
f is the frequency in MHz, C
OUT
is the capacitance in μF, L
is the inductance in μH, V
IN
is the input voltage in volts,
V
OUT
is the output voltage in volts. V
P-P
is the output
ripple in volts and I
LOAD
is the output current in amps.
C
OUT
1
ΔV
P-P,BUCK
•8•L•f
2
V
IN
–V
OUT
()
•V
OUT
V
IN
µF
()
C
OUT
I
LOAD
V
OUT
–V
IN
()
ΔV
P-P,BOOST
•V
OUT
•f
µF
()
Given that the output current is discontinuous in boost
mode, the ripple in this mode will generally be much larger
than the magnitude of the ripple in buck mode.
INPUT CAPACITOR SELECTION
It is recommended that a low ESR ceramic capacitor with a
value of at least 47μF be located as close to V
IN
as possible.
In addition, the return trace from the pin to the ground
plane should be made as short as possible. It is important
to minimize any stray resistance from the converter to the
battery or other power sources. If cabling is required to
connect the LTC3113 to the battery or power supply, a higher
ESR capacitor or a series resistor with low ESR capacitor
in parallel with the low ESR capacitor may be needed to
damp out ringing caused by the cable inductance.
CAPACITOR VENDOR INFORMATION
Both the input bypass capacitors and output capacitors
used with the LTC3113 must be low ESR and designed
to handle the large AC currents generated by switching
converters. This is important to maintain proper functioning
of the IC and to reduce output ripple. Many modern low
voltage ceramic capacitors experience signifi cant loss in
capacitance from their rated value with increased DC bias
voltages. For example, it is not uncommon for a small
surface mount ceramic capacitor to lose 50% or more
of its rated capacitance when operated near its rated
voltage. As a result, it is sometimes necessary to use
a larger value capacitance or a capacitor with a higher
voltage rating than required in order to actually realize
the intended capacitance at the full operating voltage. For
details, consult the capacitor vendors curve of capacitance
versus DC bias voltage.
LTC3113
14
3113f
APPLICATIONS INFORMATION
The capacitors listed in Table 2 provide a sampling of small
surface mount ceramic capacitors that are well suited to
LTC3113 application circuits. All listed capacitors are either
X5R or X7R dielectric in order to ensure that capacitance
loss over temperature is minimized.
Table 2. Representative Buck-Boost Surface Input Mount Bypass
and Output Capacitors
PART NUMBER
VALUE
(μF)
VOLTAGE
(V)
SIZE (mm) W × L × H
(FOOTPRINT)
AVX (www.avx.com)
1812D476KAT2A 47 6.3
3.2 × 4.5 × 2.5 (1812)
18126D107KAT2A 100 6.3
3.2 × 4.5 × 2.8 (1812)
Murata (www.murata.com)
GRM43ER60J476ME01 47 6.3
3.2 × 4.5 × 2.5 (1812)
GRM43SR60J107ME20 100 6.3
3.2 × 4.5 × 2.8 (1812)
GRM55FR60J107KA01L 100 6.3
5 × 5.7 × 3.2 (2220)
Taiyo Yuden (www.t-yuden.com)
JMK432BJ476MM-T 47 6.3
3.2 × 4.5 × 2.5 (1812)
JMK432C107MM-T 100 6.3
3.2 × 4.5 × 2.8 (1812)
TDK (www.component.tdk.com)
C4532X5R0J476M 47 6.3
3.2 × 4.5 × 2.5 (1812)
C4532X5R0J107M 100 6.3
3.2 × 4.5 × 2.5 (1812)
C5750X5R1C476M 47 16
5 × 5.7 × 2.5 (2220)
C5750X5R1A686M 68 10
5 × 5.7 × 2.5 (2220)
C5750X5R0J107M 100 6.3
5 × 5.7 × 2.5 (2220)
PCB LAYOUT CONSIDERATIONS
The LTC3113 switches large currents at high frequencies.
Special attention should be paid to the PCB layout to ensure
a stable, noise-free and effi cient application circuit. Figure
3 presents a representative 4-layer PCB layout to outline
some of the primary considerations. A few key guidelines
are outlined below:
1. All circulating high current paths should be kept as
short as possible. This can be accomplished by keeping
the routes to all highlighted components in Figure 3
as short and as wide as possible. Capacitor ground
connections should via down to the ground plane in
the shortest route possible. The bypass capacitors on
V
IN
should be placed as close to the IC as possible and
should have the shortest possible paths to ground.
2. The Exposed Pad is the power ground connection for
the LTC3113. Multiple vias should connect the backpad
directly to the ground plane. In addition maximization
of the metallization connected to the backpad will im-
prove the thermal environment and improve the power
handling capabilities of the IC. Refer to Figure 3d bot-
tom layer as an example of proper exposed pad power
ground and via layout to provide good thermal and
ground connection performance.
3. The components shown highlighted and their connec-
tions should all be placed over a complete ground plane
to minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
4. Connections to all of the components shown highlighted
should be made as wide as possible to reduce the series
resistance. This will improve effi ciency and maximize the
output current capability of the buck-boost converter.
5. To prevent large circulating currents from disrupting
the output voltage sensing, the ground for each resistor
divider should be returned to the ground plane using
a via placed close to the IC and away from the power
connections.
6. Keep the connection from the resistor dividers to the
feedback pins, FB, as short as possible and away from
the switch pin connections.
7. Crossover connections should be made on inner copper
layers if available. If it is necessary to place these on
the ground plane, make the trace on the ground plane
as short as possible to minimize the disruption to the
ground plane.
Thermal Considerations
The LTC3113 output current may need to be derated if
it is required to operate in a high ambient temperature
or delivering a large amount of continuous power. The
amount of current derating is dependent upon the input
voltage, output voltage and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by mounting the LTC3113 to a 4-layer
FR4 demo board shown in Figure 3. Boards of other sizes
and layer count can exhibit different thermal behavior, so
LTC3113
15
3113f
APPLICATIONS INFORMATION
SW1
12 13 14 15 16
1
C1
33pF
C5
F
C2
100μF
6.3V
C3
F
6.3V
V
OUT
3.3V
GND
E1
E2
R3
10k
R2
715k
1%
R7
158k
1%
3113 F03a
3
4
5
11
7
8
2
3
1
617
2
10
9
GND
R5
10k
R9
1.0M
JP1
PWM
V
IN
V
IN
V
OUT
Burst Mode
OPERATION
ON
OFF
FIXED
FREQUENCY
C8
680pF
C9
10pF
V
IN
V
IN
V
IN
RUN
BURST
RT
V
OUT
V
OUT
FB
VC
SW1 SW1
LTC3113EDHD
SW2
L1
2.2μH
SGND PGND
SW2
R8
90.9k
1%
2
3
1
JP2
C7
68μF
10V
V
IN
1.8V TO 5.5V
GND
E3
E4
R4
1M
Figure 3b. Fabrication Layer of Example PCB
Figure 3a

LTC3113EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A Wide Vin, Low Noise Buck-Boost DC/DC Converter
Lifecycle:
New from this manufacturer.
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