11
For more information www.linear.com/LTC2470
applicaTions inForMaTion
The speed bit (SPD) determines the output rate, SPD = 0
(default) for a 208sps and SPD = 1 for a 833sps output
rate. The sleep bit (SLP)
is used to power down the
on-chip reference. In the default mode, the reference re-
mains powered up at the conclusion of each conversion
cycle while the ADC is automatically powered down at the
end of each conversion cycle. If the SLP bit is set HIGH,
the reference and the ADC are powered down once the
next conversion cycle is completed. The reference and
ADC are powered up again once
CS is pulled low. The
following conversion is invalid if the next conversion is
started before the reference has started up (see Figure 3
for reference startup times as a function of compensation
capacitor and reference capacitor).
If the sleep mode is not required, SPD can be tied to GND
or V
DD
in order to simplify the user interface. It should
be noted that by tying SDI to GND, the output rate will be
set to 208sps. Tying SDI to V
DD
will result in a 833sps
output rate.
SERIAL INTERFACE
The LTC2470/LTC2472 transmit the conversion result
and receive the start of conversion command through
a synchronous 2-, 3- or 4-wire interface. This interface
can be used during the DATA OUTPUT state to read the
conversion result, program sleep and speed mode, and
to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2470/LTC2472 function with SCK idle high
(commonly known as CPOL = 1) or idle low (commonly
known as CPOL = 0).
2) After the 16th bit is read, a new conversion is started
if CS is pulled high or SCK is pulled low.
3) At any time during the Data Output state, pulling CS
high causes the part to leave the I/O state, abort the
output and begin a new conversion.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2470/
LTC2472 automatically enter the NAP mode with the ADC
powered down. The ADC’s reference will power down if the
SLP bit was set high prior to the just completed conversion
and CS is HIGH. Once CS goes low, both the reference and
ADC are powered up.
When the conversion is complete, the user applies 16
clock cycles to transfer the result. The CS rising edge is
then used to initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK).
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
D
15
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
D
14
D
13
D
12
D
2
D
1
D
0
SD0
SCK
CONVERT CONVERTNAP DATA OUTPUT
CS
SDI
EN2 SPD SLP
EN1
