15
For more information www.linear.com/LTC2470
applicaTions inForMaTion
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2470/LTC2472 into an unknown state if an SCK
pulse is missed or noise triggers an extra SCK pulse. In
this situation, it is impossible to distinguish SDO = 1 (in
-
dicating conversion in progress) from valid “1” data bits.
A method to prevent this from happening is to read 32
bits each cycle instead of 16 and ignoring the last 16 data
bits. In the case where a noisy bus leads to an unknown
SCK clock count, the extra 16 SCK clock pulses will force
a new conversion and place the device in a known state.
Driving V
CC
and GND
In relation to the V
CC
and GND pins, the LTC2470/LTC2472
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless,
the very high accuracy of this converter is best pre
-
served by careful low and high frequency power supply
decoupling.
A 0.1
µF, high quality, ceramic capacitor in parallel with
a 10µF low ESR ceramic capacitor should be connected
between the V
CC
and GND pins, as close as possible to the
package. The 0.1µF capacitor should be placed closest
to the ADC package. It is also desirable to avoid any via
in the circuit path, starting from the converter V
CC
pin,
passing through these two decoupling capacitors, and
returning to the converter GND pin. The area encompassed
by this circuit path, as well as the path length, should be
minimized.
As shown in Figure 15, REF
–
is used as the negative
reference voltage input to the ADC. This pin can be tied
directly to ground or Kelvin sensed to sensor ground. In
the case where REF
–
is used as a sense input, it should
be bypassed to ground with a 0.1μF ceramic capacitor in
parallel with a 10μF low ESR ceramic capacitor.
Very low impedance ground and power planes, and star
connections at both V
CC
and GND pins, are preferable.
The V
CC
pin should have two distinct connections: the
first to the decoupling capacitors described above, and
the second to the ground return for the power supply
voltage source.
REFOUT and COMP
The on chip 1.25V reference is internally tied to the
converter’s reference input and is output to the REFOUT
pin. A 0.1μF capacitor should be placed on the REFOUT
pin. It is possible to reduce this capacitor, but the transition
noise increases (see Figure 4). A 0.1μF capacitor should
also be placed on the COMP pin. This pin is tied to an
internal point in the reference and is used for stability.
Figure 15. LTC2470/LTC2472 Analog Input/Reference
Equivalent Circuit
R
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V
CC
V
CC
V
CC
V
CC
C
EQ
0.35pF
(TYP)
IN
+
(LTC2472)
IN
–
(LTC2472)
IN
(LTC2470)
REF
–
REFOUT
INTERNAL
REFERENCE
24702 F15
R
SW
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(TYP)
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LEAK
R
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(TYP)
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R
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