Data Sheet HMC1131
Rev. A | Page 11 of 14
APPLICATIONS INFORMATION
The HMC1131 is a GaAs, pHEMT, MMIC, medium power
amplifier consisting of four gain stages in series. V
GG
1 is the gate
bias pin for the first and second stages, while V
GG
2 is the gate
bias pin for the third and fourth stages. A simplified block
diagram is shown in Figure 31.
All measurements for this device were taken using the evaluation
printed circuit board (PCB) in its default configuration. Unless
otherwise noted, the V
GG
1, V
GG
2, and V
DD
1 to V
DD
4 pins were
tied together during measurement, respectively.
The following is the recommended bias sequence during
power-up:
1. Connect to ground.
2. Set V
GG
1 and V
GG
2 to −2 V.
3. Set V
DD
1 through V
DD
4 to 5 V.
4. Increase V
GG
1 and V
GG
2 to achieve a quiescent
I
DD
= 225 mA.
5. Apply the RF signal.
The following is the recommended bias sequence during
power-down:
1. Turn the RF signal off.
2. Decrease V
GG
1 and V
GG
2 to −2 V to achieve a quiescent
I
DD
= 0 mA (approximately).
3. Decrease V
DD
1 through V
DD
4 to 0 V.
4. Increase V
GG
1 and V
GG
2 to 0 V.
The V
DD
x = 5 V and I
DD
= 225 mA bias conditions are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC1131 at
different bias conditions may result in performance that differs
from that shown in Figure 27 and Figure 30. Biasing the
HMC1131 for higher drain current typically results in higher
P1dB, OIP3, and gain but at the expense of increased power
consumption.
13105-032
V
DD
1 V
DD
2
V
GG
1
I
DD
1
A
I
DD
1
B
RFIN
V
DD
3 V
DD
4
V
GG
2
I
DD
2
A
I
DD
2
B
RFOUT
I
DD
1 = I
DD
1
A
+ I
DD
1
B
I
DD
2 = I
DD
2
A
+ I
DD
2
B
Figure 31. Simplified Block Diagram
