1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
4 Maxim Integrated
Note 1: Specifications at T
A
= -40°C are guaranteed by design and not production tested.
Note 2: System requirement.
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to parasitically powered systems with only one device and with the minimum
1-Wire recovery times. For more heavily loaded systems, local power or an active pullup such as that found in the
DS2482-x00, DS2480B, or DS2490 may be required. If longer t
REC
is used, higher R
PUP
values may be tolerable.
Note 5: Value is 25pF maximum with local power. Maximum value represents the internal parasite capacitance when V
PUP
is first
applied. If R
PUP
= 2.2kΩ, 2.5µs after V
PUP
has been applied, the parasite capacitance does not affect normal communications.
Note 6: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function V
DD
, V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
DD
, V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower val-
ues of V
TL
, V
TH
, and V
HY
.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V
ILMAX
at all times when the master drives the line to a logic 0.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than +1V.
Note 12: Applies to a single parasitically powered DS28EA00 attached to a 1-Wire line. These values also apply to networks of
multiple DS28EA00 with local supply.
Note 13: The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 15: Interval during the negative edge on IO at the beginning of a presence-detect pulse between the time at which the voltage
is 80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
Note 16: Interval after t
RSTL
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28EA00 present.
Minimum limit is t
PDHMAX
+ t
FPDMAX
; the maximum limit is t
PDHMIN
+ t
PDLMIN
.
Note 17: ε in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18: δ in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 19: This load current is caused by the internal weak pullup, which asserts a logic 1 to the PIOB and PIOA pins. The logical
state of PIOB must not change during the execution of the Conditional Read ROM command.
Note 20: Current drawn from IO during EEPROM programming or temperature conversion interval in parasite-powered mode. The
pullup circuit on IO during the programming or temperature conversion interval should be such that the voltage at IO is
greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, then a low-impedance bypass of R
PUP
, which
can be activated during programming or temperature conversions, may need to be added. The bypass must be activated
within 10µs from the beginning of the t
PROG
or t
CONV
interval, respectively.
Note 21: The t
PROG
interval begins t
REHMAX
after the trailing rising edge on IO for the last time slot of the command byte for a valid
Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I
PROG
to I
L
(parasite power) or I
DDS
(local power).
Note 22: Write-cycle endurance is degraded as T
A
increases.
Note 23: Not 100% production tested. Guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as T
A
increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 26: The t
CONV
interval begins t
REHMAX
after the trailing rising edge on IO for the last time slot of the command byte for a valid
convert temperature sequence. The interval ends once the device’s self-timed temperature conversion cycle is complete
and the current drawn by the device has returned from I
CONV
to I
L
(parasite power) or I
DDS
(local power).
Note 27: Drift data is preliminary and based on a 1000-hour stress test performed on another device with comparable design and
fabricated in the same manufacturing process. This test was performed at greater than +85°C with V
DD
= +5.5V.
Confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test.
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
