MT89L80 Data Sheet
13
Zarlink Semiconductor Inc.
Figure 13 - Serial Inputs
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
†
- Processor Bus (Figures 14)
Characteristics Sym Min Typ
‡
Max Units Test Conditions
1 Chip Select Setup Time t
CSS
0ns
2 Read/Write Setup Time t
RWS
5ns
3 Address Setup Time t
ADS
5ns
4 Acknowledgment Delay
Control Register Read
t
AKD
52 120 ns C
L
=150 pF
Control Register Write t
AKD
25 65 ns C
L
=150 pF
Connection Memory Read t
AKD
62 120 ns C
L
=150 pF
Connection Memory Write t
AKD
30 53 ns C
L
=150 pF
Data Memory Read t
AKD
560 1220 ns C
L
=150 pF
5 Fast Write Data Setup Time t
FWS
0ns
6 Slow Write Data Delay t
SWD
122 ns
7 Read Data Setup Time t
RDS
0nsC
L
= 150 pF
8 Data Hold Time Read
Write
t
DHT
10 90 ns R
L
=1 KΩ
∗
, C
L
=150 pF
t
DHT
510 ns
9 Read Data To High Impedance t
RDZ
15 50 90 ns R
L
=1 KΩ
∗
, C
L
=150 pF
10 Chip Select Hold Time t
CSH
0ns
11 Read/Write Hold Time t
RWH
0ns
12 Address Hold Time t
ADH
8ns
13 Acknowledgment Hold Time t
AKH
50 80 ns R
L
=1 KΩ
∗
, C
L
=150 pF
Bit Cell Boundaries
C4i
STi0
to
STi7
t
SIS
t
SIH
V
HM
V
LM
V
HM
V
LM
