MT89L80APR1 Datasheet MT89L80AP1, MT89L80APR1, MT89L80ANR1 | P4-P6

MT89L80 Data Sheet

Zarlink Semiconductor Inc.

The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames

which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key

device being the MT89L80 chip.

The MT89L80 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and

simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-

BUS outputs (Message Mode). To the microprocessor, the MT89L80 looks like a memory peripheral. The

microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and

output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the

microprocessor can receive messages from ST-BUS input channels or check which switched connections have

already been established.

By integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed

processing and to switch voice or data in an ST-BUS architecture.

Hardware Description

Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the

eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel

containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g.,

Zarlink’s MT8964).

This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data

Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read

by the microprocessor which controls the chip.

Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS

output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either

be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,

then the contents of the Connection Memory Low location associated with the output channel is used to address

the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the

data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),

then the contents of the Connection Memory Low location associated with the output channel are output directly,

and this data is output repetitively on the channel once every frame until the microprocessor intervenes.

The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives

address information at A5 to A0 and handles the microprocessor control signals CS

, DTA, R/W and DS. There are

two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control

lines directly.

The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel

into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the

Connection Memory Low. The Connection Memory High determines whether individual output channels are in

Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of

MT89L80s to be constructed. It also controls the CSTo pin.

All ST-BUS timing is derived from the two signals C4i

and F0i.

MT89L80 Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - Address Memory Map

Software Control

The address lines on the Control Interface give access to the Control Register directly or, depending on the

contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.

If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If

A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory

and stream selected in the Control Register.

The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see

Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and

the stream address bits define one of the ST-BUS input or output streams.

Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the

Connection Memory Low.

The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,

the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the

ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,

regardless of the actual values.

A5 A4 A3 A2 A1 A0 Hex Address Location

•

00 - 1F

•

Control Register *

Channel 0

†

Channel 1

†

•

Channel 31

†

* Writing to the Control Register is the only fast transaction.

†

Memory and stream are specified by the contents of the Control Register.

Bit Name Description

7 Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection

Memory Low, except when the Control Register is accessed again. When 0, the Memory

Select bits specify the memory for subsequent operations. In either case, the Stream

Address Bits select the subsection of the memory which is made available.

76 5432 10

Mode

Control

Bits

(unused)

Memory

Select

Bits

Stream

Address

Bits

MT89L80 Data Sheet

Zarlink Semiconductor Inc.

Figure 4 - Control Register Bits

Figure 5 - Connection Memory High Bits

6 Message

Mode

When 1, the contents of the Connection Memory Low are output on the Serial Output

streams except when the ODE pin is low. When 0, the Connection Memory bits for each

channel determine what is output.

5 (unused)

4-3 Memory

Select Bits

0-0 - Not to be used

0-1 - Data Memory (read only from the microprocessor port)

1-0 - Connection Memory Low

1-1 - Connection Memory High

2-0 Stream

Address Bits

The number expressed in binary notation on these bits refers to the input or output ST-BUS

stream which corresponds to the subsection of memory made accessible for subsequent

operations.

Bit Name Description

2 Message

Channel

When 1, the contents of the corresponding location in Connection Memory Low are

output on the location’s channel and stream. When 0, the contents of the corresponding

location in Connection Memory Low act as an address for the Data Memory and so

determine the source of the connection to the location’s channel and stream.

1 CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output

first.

0 Output

Enable

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the

output driver for the location’s channel and stream. This allows individual channels on

individual streams to be made high-impedance, allowing switching matrices to be

constructed. A 1 enables the driver and a 0 disables it.

Bit Name Description

76 5432 10

Mode

Control

Bits

(unused)

Memory

Select

Bits

Stream

Address

Bits

76 5432 10

No Corresponding Memory

- These bits give 0s if read.

Per Channel

Control Bits

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MT89L80APR1

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