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EVAL-AVB-LISTENER

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADV7612 Data Sheet
Rev. E | Page 12 of 20
FUNCTIONAL OVERVIEW
HDMI RECEIVER
The HDMI receiver supports all mandatory and many optional
3D formats, HDTV formats up to 1080p, and all display resolutions
up to UXGA (1600 × 1200 at 60 Hz).
With the inclusion of HDCP, displays can now receive encrypted
video content. The HDMI interface of the ADV7612 allows for
authentication of a video receiver, decryption of encoded data
at the receiver, and renewability of that authentication during
transmission, as specified by the HDCP 1.4 protocol.
The HDMI-compatible receiver on the ADV7612 allows program-
mable equalization of the HDMI data signals. This equalization
compensates for the high frequency losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies.
It is capable of equalizing for cable lengths up to 30 meters to
achieve robust receiver performance.
The ADV7612 has a synchronization regeneration block used
to regenerate the DE based on the measurement of the video
format being displayed, and to filter the horizontal and vertical
synchronization signals to prevent glitches.
The HDMI receiver also supports TERC4 error detection, used for
detection of corrupted HDMI packets following a cable disconnect.
The HDMI receiver offers advanced audio functionality. The
receiver contains an audio mute controller that can detect a
variety of conditions, which may result in audible extraneous
noise in the audio output. On detection of these conditions, the
audio signal can be ramped to prevent audio clicks or pops.
Audio output can be formatted to one of the following modes:
• LPCM and IEC 61937 S/PDIF
• DSD audio
• DST audio
• HBR audio
Xpressview fast switching can be implemented with full HDCP
authentication available on the background port. Synchro-
nization measurement and status information are available
for the background port.
HDMI receiver features include:
• 2:1 multiplexed HDMI receiver
• 3D format support
• 225 MHz HDMI receiver
• Integrated equalizer for cable lengths up to 30 meters
• HDCP 1.4 also on background ports
• Internal HDCP keys
• 36-/30-bit Deep Color support
• PCM, HBR, DST, and DSD audio packet support
• Repeater support
• Internal EDID RAM
• Hot Plug assert output pin for each HDMI port
• CEC controller
COMPONENT PROCESSOR
The ADV7612 has an any-to-any 3 × 3 CSC matrix. The CSC
block is placed at the back of the CP section. CSC enables
YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other
standards of color space can be implemented using the color
space converter.
CP features include:
• 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other
HDTV formats are supported
• Manual adjustments including gain (contrast) and
offset (brightness), hue, and saturation
• Free run output mode that provides stable timing when no
video input is present
• 170 MHz conversion rate, which supports RGB input
resolutions up to 1600 × 1200 at 60 Hz
• Contrast, brightness, hue, and saturation controls
• Standard identification enabled by STDI block
• RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for video-centric back end IC
interfacing
• DE output signal supplied for direct connection to
HDMI/DVI transmitter
OTHER FEATURES
The ADV7612 has HS, VS, FIELD, and DE output signals with
programmable position, polarity, and width.
The ADV7612 has two programmable interrupt request output
pins, including INT1 and INT2 (INT2 is accessible only via one
of following pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2).
It also features a low power-down mode. The I
2
C address of the
main map is 0x98 after reset. This can be changed after reset
to 0x9A if pullup is attached to VS/FIELD/ALSB pin and I
2
C
command SAMPLE_ALSB is issued. Refer to the Register
Access and Serial Ports Description section in the UG-216.
The ADV7612 is provided in a 14 mm × 14 mm, RoHS-compliant
LQFP_EP package, and is specified over the −40°C to +85°C
temperature range.
Data Sheet ADV7612
Rev. E | Page 13 of 20
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7612 is highly flexible. The pixel
output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4
RGB. The pixel data supports both single and double data rates
modes
1
. In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit
4:4:4 output is possible. In DDR mode, the pixel output port can
be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB.
Bus rotation is supported. Table 5 to Table 8 outline the different
output formats that are supported. All output modes are controlled
via I
2
C.
1
DDR mode is only supported only up to 50 MHz (an equivalent to data rate
clocked 100 MHz clock in SDR mode).
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include the following:
8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded
time codes and/or HS, VS, and FIELD output signals
16-/20-/24-bit YCrCb with embedded time codes and/or
HS and VS/FIELD pin timing
24-/30-/36-bit YCrCb/RGB with embedded time codes
and/or HS and VS/FIELD pin timing
DDR 8-/10-/12-bit 4:2:2 YCrCb
DDR 12-/24-/30-/36 bit 4:4:4 RGB
Table 5. SDR 4:2:2 Output Modes
SDR 4:2:2
OP_FORMAT_SEL[7:0] 0x0
1
0x1 0x2 0x6 0x0A
Pixel Output
8-Bit SDR
ITU-R BT.656
Mode 0
10-Bit SDR
ITU-R BT.656
Mode 0
12-Bit SDR
ITU-R BT.656
Mode 0
12-Bit SDR
ITU-R BT.656
Mode 1
12-Bit SDR
ITU-R BT.656
Mode 2
P35 High-Z High-Z High-Z High-Z Y3, Cb3, Cr3
P34 High-Z High-Z High-Z High-Z Y2, Cb2, Cr2
P33 High-Z High-Z High-Z High-Z Y1, Cb1, Cr1
P32 High-Z High-Z High-Z High-Z Y0, Cb0, Cr0
P31 High-Z High-Z High-Z High-Z High-Z
P30 High-Z High-Z High-Z High-Z High-Z
P29 High-Z High-Z High-Z Y1, Cb1, Cr1 High-Z
P28 High-Z High-Z High-Z Y0, Cb0, Cr0 High-Z
P27 High-Z High-Z High-Z High-Z High-Z
P26 High-Z High-Z High-Z High-Z High-Z
P25 High-Z High-Z High-Z High-Z High-Z
P24 High-Z High-Z High-Z High-Z High-Z
P23 Y7, Cb7, Cr7 Y9, Cb9, Cr9 Y11, Cb11, Cr11 Y11, Cb11, Cr11 Y11, Cb11, Cr11
P22 Y6, Cb6, Cr6 Y8, Cb8, Cr8 Y10, Cb10, Cr10 Y10, Cb10, Cr10 Y10, Cb10, Cr10
P21 Y5, Cb5, Cr5 Y7, Cb7, Cr7 Y9, Cb9, Cr9 Y9, Cb9, Cr9 Y9, Cb9, Cr9
P20 Y4, Cb4, Cr4 Y6, Cb6, Cr6 Y8, Cb8, Cr8 Y8, Cb8, Cr8 Y8, Cb8, Cr8
P19 Y3, Cb3, Cr3 Y5, Cb5, Cr5 Y7, Cb7, Cr7 Y7, Cb7, Cr7 Y7, Cb7, Cr7
P18 Y2, Cb2, Cr2 Y4, Cb4, Cr4 Y6, Cb6, Cr6 Y6, Cb6, Cr6 Y6, Cb6, Cr6
P17 Y1, Cb1, Cr1 Y3, Cb3, Cr3 Y5, Cb5, Cr5 Y5, Cb5, Cr5 Y5, Cb5, Cr5
P16 Y0, Cb0, Cr0 Y2, Cb2, Cr2 Y4, Cb4, Cr4 Y4, Cb4, Cr4 Y4, Cb4, Cr4
P15 High-Z Y1, Cb1, Cr1 Y3, Cb3, Cr3 Y3, Cb3, Cr3 High-Z
P14 High-Z Y0, Cb0, Cr0 Y2, Cb2, Cr2 Y2, Cb2, Cr2 High-Z
P13 High-Z High-Z Y1, Cb1, Cr1 High-Z High-Z
P12 High-Z High-Z Y0, Cb0, Cr0 High-Z High-Z
P11 High-Z High-Z High-Z High-Z High-Z
P10 High-Z High-Z High-Z High-Z High-Z
P9 High-Z High-Z High-Z High-Z High-Z
P8 High-Z High-Z High-Z High-Z High-Z
P7 High-Z High-Z High-Z High-Z High-Z
P6 High-Z High-Z High-Z High-Z High-Z
P5 High-Z High-Z High-Z High-Z High-Z
P4 High-Z High-Z High-Z High-Z High-Z
P3 High-Z High-Z High-Z High-Z High-Z
P2 High-Z High-Z High-Z High-Z High-Z
P1 High-Z High-Z High-Z High-Z High-Z
P0 High-Z High-Z High-Z High-Z High-Z
1
Modes 0x00, 0x01, 0x02, 0x06 and 0x0A require additional writes to IO Map reg. 0x19[7:6]=2’b11 and IO Map reg.0x33[6]=1
ADV7612 Data Sheet
Rev. E | Page 14 of 20
Table 6. SDR 4:2:2 and 4:4:4 Output Modes
SDR 4:2:2 SDR 4:4:4
OP_FORMAT_SEL[7:0] 0x80 0x81 0x82 0x86 0x8A 0x40 0x41 0x42 0x46
Pixel Output
16-Bit SDR
ITU-R BT.656
4:2:2 Mode 0
20-Bit
SDR ITU-R
BT.656 4:2:2
Mode 0
24-Bit SDR
ITU-R
BT.656
4:2:2
Mode 0
24-Bit SDR
ITU-R
BT.656
4:2:2
Mode 1
24-Bit SDR
ITU-R
BT.656
4:2:2
Mode 2
24-Bit
SDR
4:4:4
Mode 0
30-Bit
SDR
4:4:4
Mode 0
36-Bit
SDR
4:4:4
Mode 0
36-Bit
SDR
4:4:4
Mode 1
P35 High-Z High-Z High-Z High-Z Y3 R7 R9 R11 R9
P34 High-Z High-Z High-Z High-Z Y2 R6 R8 R10 R8
P33 High-Z High-Z High-Z Cb1, Cr1 Y1 R5 R7 R9 R7
P32 High-Z High-Z High-Z Cb0, Cr0 Y0 R4 R6 R8 R6
P31 High-Z High-Z High-Z High-Z Cb3, Cr3 R3 R5 R7 R5
P30 High-Z High-Z High-Z High-Z Cb2, Cr2 R2 R4 R6 R4
P29 High-Z High-Z High-Z Y1 Cb1, Cr1 R1 R3 R5 R3
P28 High-Z High-Z High-Z Y0 Cb0, Cr0 R0 R2 R4 R2
P27 High-Z High-Z High-Z High-Z High-Z High-Z R1 R3 R1
P26 High-Z High-Z High-Z High-Z High-Z High-Z R0 R2 R0
P25 High-Z High-Z High-Z High-Z High-Z High-Z High-Z R1 G7
P24 High-Z High-Z High-Z High-Z High-Z High-Z High-Z R0 G6
P23 Y7 Y9 Y11 Y11 Y11 G7 G9 G11 G5
P22 Y6 Y8 Y10 Y10 Y10 G6 G8 G10 G4
P21 Y5 Y7 Y9 Y9 Y9 G5 G7 G9 G3
P20 Y4 Y6 Y8 Y8 Y8 G4 G6 G8 G2
P19 Y3 Y5 Y7 Y7 Y7 G3 G5 G7 G1
P18 Y2 Y4 Y6 Y6 Y6 G2 G4 G6 G0
P17 Y1 Y3 Y5 Y5 Y5 G1 G3 G5 B11
P16 Y0 Y2 Y4 Y4 Y4 G0 G2 G4 B10
P15 High-Z Y1 Y3 Y3 High-Z High-Z G1 G3 B9
P14 High-Z Y0 Y2 Y2 High-Z High-Z G0 G2 B8
P13 High-Z High-Z Y1 High-Z High-Z High-Z High-Z G1 G11
P12 High-Z High-Z Y0 High-Z High-Z High-Z High-Z G0 G10
P11 Cb7, Cr7 Cb9, Cr9 Cb11, Cr11 Cb11, Cr11 Cb11, Cr11 B7 B9 B11 B7
P10 Cb6, Cr6 Cb8, Cr8 Cb10, Cr10 Cb10, Cr10 Cb10, Cr10 B6 B8 B10 B6
P9 Cb5, Cr5 Cb7, Cr7 Cb9, Cr9 Cb9, Cr9 Cb9, Cr9 B5 B7 B9 B5
P8 Cb4, Cr4 Cb6, Cr6 Cb8, Cr8 Cb8, Cr8 Cb8, Cr8 B4 B6 B8 B4
P7 Cb3, Cr3 Cb5, Cr5 Cb7, Cr7 Cb7, Cr7 Cb7, Cr7 B3 B5 B7 B3
P6 Cb2, Cr2 Cb4, Cr4 Cb6, Cr6 Cb6, Cr6 Cb6, Cr6 B2 B4 B6 B2
P5 Cb1, Cr1 Cb3, Cr3 Cb5, Cr5 Cb5, Cr5 Cb5, Cr5 B1 B3 B5 B1
P4 Cb0, Cr0 Cb2, Cr2 Cb4, Cr4 Cb4, Cr4 Cb4, Cr4 B0 B2 B4 B0
P3 High-Z Cb1, Cr1 Cb3, Cr3 Cb3, Cr3 High-Z High-Z B1 B3 R11
P2 High-Z Cb0, Cr0 Cb2, Cr2 Cb2, Cr2 High-Z High-Z B0 B2 R10
P1 High-Z High-Z Cb1, Cr1 High-Z High-Z High-Z High-Z B1 G9
P0 High-Z High-Z Cb0, Cr0 High-Z High-Z High-Z High-Z B0 G8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

EVAL-AVB-LISTENER

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Manufacturer:
Analog Devices Inc.
Description:
Video IC Development Tools EVAL-AVB-LISTENER
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