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ADF4216BRU-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADF4216/ADF4217/ADF4218
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Dual RF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
22-BIT
DATA
REGISTER
SDOUT
OSCILLATOR
CLOCK
DATA
LE
IF
LOCK
DETECT
MUXOUT
ADF4216/ADF4217/ADF4218
CP
RF
CP
IF
CHARGE
PUMP
PHASE
COMPARATOR
OUTPUT
MUX
REF
IN
RF
PRESCALER
RF
IN
A
CHARGE
PUMP
PHASE
COMPARATOR
RF
LOCK
DETECT
V
DD
1V
DD
2V
P
1V
P
2
AGND
RF
DGND
RF
DGND
IF
AGND
IF
RF
IN
B
DGND
IF
IF
PRESCALER
IF
IN
A
11-BIT IF
B-COUNTER
6-BIT IF
A-COUNTER
IF
IN
B
N = BP + A
N = BP + A
14-BIT IF
R-COUNTER
14-BIT IF
R-COUNTER
11-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
FEATURES
ADF4216: 550 MHz/1.2 GHz
ADF4217: 550 MHz/2.0 GHz
ADF4218: 550 MHz/2.5 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Currents
Selectable Dual Modulus Prescaler
IF: 8/9 or 16/17
RF: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4216/ADF4217/ADF4218 are dual frequency synthe-
sizers that can be used to implement local oscillators (LOs) in
the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus prescaler
(P/P+1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizers are
used with an external loop filter and VCOs (Voltage Con-
trolled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
REV. 0
–2–
ADF4216/ADF4217/ADF4218–SPECIFICATIONS
1
(V
DD
1 = V
DD
2 = 3 V ⴞ 10%, 5 V ⴞ 10%;
V
DD
1, V
DD
2 ⱕ V
P
1, V
P
2 ⱕ 6.0 V
; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; T
A
= T
MIN
to T
MAX
unless otherwise noted.)
P
arameter B Version B Chips
2
Unit Test Conditions/Comments
RF/IF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
) See Figure 3 for Input Circuit.
ADF4216 0.2/1.2 0.2/1.2 GHz min/max For lower frequency operation (below the
ADF4217 0.2/2.0 0.2/2.0 GHz min/max minimum stated) use a square wave source.
ADF4218 0.5/2.5 0.5/2.5 GHz min/max
IF Input Frequency (IF
IN
) 45/550 45/550 MHz min/max
RF Input Sensitivity –15/+4 –15/+4 dBm min/max
IF Input Sensitivity –10/+4 –10/+4 dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
165 165 MHz max
RF/IF CHARACTERISTICS (5 V)
RF Input Frequency (RF
IN
) See Figure 3 for Input Circuit.
ADF4216 0.2/1.2 0.2/1.2 GHz min/max For lower frequency operation (below the
ADF4217 0.2/2.0 0.2/2.0 GHz min/max minimum stated) use a square wave source.
ADF4218 0.5/2.5 0.5/2.5 GHz min/max
IF Input Frequency (IF
IN
) 25/550 25/550 MHz min/max
RF Input Sensitivity –15/+4 –15/+4 dBm min/max
IF Input Sensitivity –10/+4 –10/+4 dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
200 200 MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency 5/40 5/40 MHz min/max For f < 5 MHz, use dc-coupled square wave
(0 to V
DD
).
REFIN Input Sensitivity
4
0.5 0.5 V p-p min AC-Coupled. When DC-Coupled:
0 to V
DD
max (CMOS-Compatible)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
5
40 40 MHz max
CHARGE PUMP
I
CP
Sink/Source
High Value 4.5 4.5 mA typ
Low Value 1.125 1.125 mA typ
Absolute Accuracy 1 1 % typ
I
CP
Three-State Leakage Current 1 1 nA typ
Sink and Source Current Matching 1 1 % typ
I
CP
vs. V
CP
10 10 % max 0.5 V ⱕ V
CP
ⱕ V
P
– 0.5 V
I
CP
vs. Temperature 10 10 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 0.8 × V
DD
0.8 × V
DD
V min
V
INL
, Input Low Voltage 0.2 × V
DD
0.2 × V
DD
V max
I
INH
/I
INL
, Input Current ± 1 ± 1 µA max
C
IN
, Input Capacitance 10 10 pF max
Oscillator Input Current ± 100 ± 100 µA max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
– 0.4 V
DD
– 0.4 V min I
OH
= 500 µA
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
V
DD
1 2.7/5.5 2.7/5.5 V min/V max
V
DD
2V
DD
1V
DD
1
V
P
V
DD
1/6.0 V
DD
1/6.0 V min/V max AV
DD
ⱕ V
P
ⱕ 6.0 V
REV. 0
–3–
ADF4216/ADF4217/ADF4218
Parameter B Version B Chips
2
Unit Test Conditions/Comments
POWER SUPPLIES (Continued)
I
DD
(RF + IF)
6
See TPC 22 and TPC 23
ADF4216 18 9 mA max 9.0 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4217 21 12 mA max 12 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4218 25 14 mA max 14 mA typical at V
DD
= 3 V and T
A
= 25°C
I
DD
(RF Only)
ADF4216 10 5 mA max 5.0 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4217 14 7 mA max 7.0 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4218 18 9 mA max 9.0 mA typical at V
DD
= 3 V and T
A
= 25°C
I
DD
(IF Only)
ADF4216 9 4.5 mA max 4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4217 9 4.5 mA max 4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
ADF4218 9 4.5 mA max 4.5 mA typical at V
DD
= 3 V and T
A
= 25°C
I
P
(I
P
1 + I
P
2) 0.6 0.6 mA max T
A
= 25°C
Low-Power Sleep Mode 5 5 µA max 0.5 µA typical
NOISE CHARACTERISTICS
Phase Noise Floor
7
–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency
Phase Noise Performance
8
@ VCO Output
ADF4216, ADF4217, ADF4218 (IF)
9
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4216 (RF): 900 MHz Output
10
–87 –87 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4217 (RF): 900 MHz Output
10
–88 –88 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4218 (RF): 900 MHz Output
10
–90 –90 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4216 (RF): 836 MHz Output
11
–78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency
ADF4217 (RF): 1750 MHz Output
12
–85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4217 (RF): 1750 MHz Output
13
–66 –66 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency
ADF4218 (RF): 1960 MHz Output
14
–84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
Spurious Signals
ADF4216 ADF4217, ADF4218 (IF)
9
–97/–106 –97/–106 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4216 (RF): 900 MHz Output
10
–98/–106 –98/–106 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4217 (RF): 900 MHz Output
10
–91/–100 –91/–100 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4218 (RF): 900 MHz Output
10
–80/–84 –80/–84 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4216 (RF): 836 MHz Output
11
–80/–84 –80/–84 dB typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency
ADF4217 (RF): 1750 MHz Output
12
–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4217 (RF): 1750 MHz Output
13
–65/–73 –65/–73 dB typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency
ADF4218 (RF): 1960 MHz Output
14
–80/–84 –80/–84 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
P = 16; RF
IN
= 900 MHz; IF
IN
= 540 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 300 Hz; f
RF
= 836 MHz; N = 27867; Loop B/W = 3 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Specifications subject to change without notice.
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ADF4216BRU-REEL

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IC PLL FREQ SYNTHESIZER 20-TSSOP
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