REV. 0
ADF4216/ADF4217/ADF4218
–4–
TIMING CHARACTERISTICS
Limit at
T
MIN
to T
MAX
Parameter (B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK Setup Time
t
2
10 ns min DATA to CLOCK Hold Time
t
3
25 ns min CLOCK High Duration
t
4
25 ns min CLOCK Low Duration
t
5
10 ns min CLOCK to LE Setup Time
t
6
20 ns min LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
CLOCK
DATA
LE
LE
DB21 (MSB)
DB20
DB2
DB1
(CONTROL BIT C2)
t
1
t
2
t
3
t
4
t
6
t
5
DB0 (LSB)
(CONTROL BIT C1)
Figure 1. Timing Diagram
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
P
1, V
P
2 = V
DD
,
5 V 10%; AGND = DGND = 0 V;
T
A
= T
MIN
to T
MAX
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B,
IF
IN
A, IF
IN
B to GND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θ
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model Temperature Range Package Description Package Option*
ADF4216BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4217BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4218BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
*Contact the factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADF4216/ADF4217/ADF4218
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1V
DD
1 Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1 must
have the same potential as V
DD
2.
2V
P
1 Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
.
3CP
RF
Output from the RF Charge Pump. When enabled this provides ± I
CP
to the external loop filter, which in
turn drives the external VCO.
4 DGND
RF
Ground Pin for the RF Digital Circuitry.
5RF
IN
A Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
6RF
IN
B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
7 AGND
RF
Ground Pin for the RF Analog Circuitry.
8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resis-
tance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 DGND
IF
Ground Pin for the IF Digital (Interface and Control Circuitry).
10 MUXOUT This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Fre-
quency to be accessed externally. See Table V.
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high impedance CMOS input.
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
14 AGND
IF
Ground Pin for the IF Analog Circuitry.
15 IF
IN
B Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
16 IF
IN
A Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
17 DGND
IF
Ground Pin for the IF Digital, Interface, and Control Circuitry.
18 CP
IF
Output from the IF Charge Pump. When enabled this provides ± I
CP
to the external loop filter, which in turn
drives the external VCO.
19 V
P
2 Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
.
20 V
DD
2 Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. V
DD
2 should have a value of between 2.7 V
and 5.5 V. V
DD
2 must have the same potential as V
DD
1.
PIN CONFIGURATION
REF
IN
CLK
DATA
LE
MUXOUT
RF
IN
A
CP
RF
AGND
RF
RF
IN
B
V
DD
1
DGND
RF
V
DD
2
V
P
1
DGND
IF
AGND
IF
IF
IN
B
IF
IN
A
DGND
IF
CP
IF
V
P
2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TSSOP
ADF4216/
ADF4217/
ADF4218
REV. 0
ADF4216/ADF4217/ADF4218
–6–
Typical Performance Characteristics
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
GHz S MA R 50
FREQ MAGS11 ANGS11
1.35 0.816886959 51.80711782
1.45 0.825983016 56.20373378
1.55 0.791737125 61.21554647
1.65 0.770543186 61.88187496
1.75 0.793897072 65.39516615
1.85 0.745765233 69.24884474
1.95 0.7517547 71.21608147
2.05 0.745594889 75.93169947
2.15 0.713387801 78.8391674
2.25 0.711578577 81.71934806
2.35 0.698487131 85.49067481
2.45 0.669871818 88.41958754
2.55 0.668353367 91.70921678
FREQ MAGS11 ANGS11
0.0 0.957111193 3.130429321
0.15 0.963546793 6.686426265
0.25 0.953621785 11.19913586
0.35 0.953757706 15.35637483
0.45 0.929831379 20.3793432
0.55 0.908459709 22.69144845
0.65 0.897303634 27.07001443
0.75 0.876862863 31.32240763
0.85 0.849338092 33.68058163
0.95 0.858403269 38.57674885
1.05 0.841888714 41.48606772
1.15 0.840354983 45.97597958
1.25 0.822165839 49.19163116
TPC 1. S-Parameter Data for the AD4218 RF Input
(Up to 2.5 GHz)
RF INPUT FREQUENCY GHz
0
2
1
1.5
35
RF INPUT POWER dBm
0
15
20
25
30
5
10
0.5
V
DD
= 3.3V
V
P
= 3.3V
T
A
= +85C
T
A
= +25C
T
A
= 40C
2.5
3
TPC 2. Input Sensitivity for the ADF4218 (RF)
2kHz 1kHz 900MHz +1kHz +2kHz
V
DD
= 3V, V
P
= 5V
I
CP
= 4.375mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
REFERENCE
LEVEL = 4.2dBm
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
90dBc/Hz
TPC 3. ADF4218 RF Phase Noise (900 MHz, 200 kHz, 20 kHz)
400kHz 200kHz 900MHz +200kHz +400kHz
V
DD
= 3V, V
P
= 5V
I
CP
= 4.375mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
REFERENCE
LEVEL = 4.2dBm
90dBc
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
TPC 4. ADF4218 RF Reference Spurs (900 MHz, 200 kHz,
20 kHz)
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.55
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
0.55 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
TPC 5. ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.65
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
0.65 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
TPC 6. ADF4218 RF Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)

ADF4216BRU-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC PLL FREQ SYNTHESIZER 20-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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