MAX7311AAG+ Datasheet MAX7311ATG+T, MAX7311AUG+, MAX7311ATG+ | P10-P12

MAX7311

Data is clocked into a register on the falling edge of the

acknowledge clock pulse. After reading the first byte,

additional bytes may be read and reflect the content in

the other register in the pair. For example, if input port 1

is read, the next byte read is input port 2. An unlimited

number of data bytes can be read in one read trans-

mission, but the final byte received must not be

acknowledged by the bus master.

Interrupt (

INT

)

The open-drain interrupt output, INT, activates when

one of the port pins changes states and only when the

pin is configured as an input. The interrupt deactivates

when the input returns to its previous state or the input

put does not cause an interrupt. Each 8-bit port register

is read independently; therefore, an interrupt caused

by port 1 is not cleared by a read of port 2’s register.

Changing an I/O from an output to an input may cause

a false interrupt to occur if the state of that I/O does not

match the content of the input port register.

Input/Output Port

When an I/O is configured as an input, FETs Q1 and Q2

are off (Figure 10), creating a high-impedance input with

a nominal 100kΩ pullup to V

. All inputs are overvoltage

protected to 5.5V, independent of supply voltage. When

a port is configured as an output, either Q1 or Q2 is on,

depending on the state of the output port register. When

powers up, an internal power-on reset sets all regis-

ters to their respective defaults (Table 1).

Input Port Registers

The input port registers (Table 2) are read-only ports.

They reflect the incoming logic levels of the pins,

regardless of whether the pin is defined as an input or

an output by the respective configuration register. A

read of the input port 1 register latches the current

value of I/O0–I/O7. A read of the input port 2 register

latches the current value of I/O8–I/O15. Writes to the

input port registers are ignored.

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

10 ______________________________________________________________________________________

SET

CLR

SET

CLR

DATA FROM

SHIFT REGISTER

WRITE

CONFIGURATION

PULSE

DATA FROM

SHIFT REGISTER

WRITE PULSE

READ PULSE

OUTPUT PORT

SET

CLR

POLARITY INVERSION

POLARITY

DATA

SET

CLR

INPUT PORT

CONFIGURATION

100kΩ

DATA FROM

SHIFT REGISTER

WRITE POLARITY

PULSE

POWER-ON

RESET

TO INT

INPUT PORT

I/O PIN

OUTPUT PORT

Figure 10. Simplified Schematic of I/Os

Output Port Registers

The output port registers (Table 3) set the outgoing

logic levels of the I/Os defined as outputs by the

respective configuration register. Reads from the out-

put port registers reflect the value that is in the flip-flop

controlling the output selection, not the actual I/O value.

Polarity Inversion Registers

The polarity inversion registers (Table 4) enable polarity

inversion of pins defined as inputs by the respective

port configuration registers. Set the bit in the polarity

inversion register to invert the corresponding port pin’s

polarity. Clear the bit in the polarity inversion register to

retain the corresponding port pin’s original polarity.

Configuration Registers

The configuration registers (Table 5) configure the

directions of the I/O pins. Set the bit in the respective

configuration register to enable the corresponding port

as an input. Clear the bit in the configuration register to

enable the corresponding port as an output.

Bus Timeout

Set register 0x08 LSB (bit 0) to enable the bus timeout

function (Table 6) or clear it to disable the bus timeout

function. Enabling the timeout feature resets the

MAX7311 serial bus interface when SCL stops either high

or low during a read or write. If either SCL or SDA is low

for more than 29ms after the start of a valid serial transfer,

the interface resets itself and sets up SDA as an input.

The MAX7311 then waits for another START condition.

Standby

The MAX7311 goes into standby when the I

C bus is

idle. Standby supply current is typically 2.9µA.

Applications Information

Hot Insertion

The I/O ports I/O0–I/O15, interrupt output INT, and serial

interface SDA, SCL, AD0–2 remain high impedance with

up to 6V asserted on them when the MAX7311 is pow-

ered down (V+ = 0V). The MAX7311 can therefore be

used in hot-swap applications. Note that each I/O’s

100kΩ pullup effectively becomes a 100kΩ pulldown

when the MAX7311 is powered down.

Power-Supply Consideration

The MAX7311 operates from a supply voltage of 2V to

5.5V. Bypass the power supply to GND with a 0.047µF

capacitor as close to the device as possible. For the

QFN version, connect the exposed pad to GND.

MAX7311

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

______________________________________________________________________________________ 11

I7 I6 I5 I4 I3 I2 I1 I0

BIT

I15 I14 I13 I12 I11 I10 I9 I8

Table 2. Registers 0x00, 0x01—Input Port Registers

O7 O6 O5 O4 O3 O2 O1 O0

BIT

O15 O14 O13 O12 O11 O10 O9 O8

Power-up default 1 1111111

Table 3. Registers 0x02, 0x03—Output Port Registers

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

BIT

I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8

Power-up default 0 0000000

Table 4. Registers 0x04, 0x05—Polarity Inversion Registers

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

BIT

I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8

Power-up default 1 1 1 1 1 1 1 1

Table 5. Registers 0x06, 0x07—Configuration Registers

BIT 76543210

Power-up default 00000001

Table 6. Register 0x08—Timeout Register

MAX7311

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

12 ______________________________________________________________________________________

AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 ADDRESS (HEX)

GNDSCLGND0010000 0x20

GND SCL V

0010001 0x22

GNDSDAGND0010010 0x24

GND SDA V

0010011 0x26

SCLGND0010100 0x28

SCL V

0010101 0x2A

SDAGND0010110 0x2C

SDA V

0010111 0x2E

GNDSCLSCL0011000 0x30

GNDSCLSDA0011001 0x32

GNDSDASCL0011010 0x34

GNDSDASDA0011011 0x36

SCLSCL0011100 0x38

SCLSDA0011101 0x3A

SDASCL0011110 0x3C

SDASDA0011111 0x3E

GNDGNDGND0100000 0x40

GND GND V

0100001 0x42

GND V

GND0100010 0x44

GND V

0100011 0x46

GNDGND0100100 0x48

GND V

0100101 0x4A

GND0100110 0x4C

0100111 0x4E

GNDGNDSCL0101000 0x50

GNDGNDSDA0101001 0x52

GND V

SCL0101010 0x54

GND V

SDA0101011 0x56

GNDSCL0101100 0x58

GNDSDA0101101 0x5A

SCL0101110 0x5C

SDA0101111 0x5E

Table 7. MAX7311 Address Map

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX7311AAG+

Mfr. #:

Buy MAX7311AAG+

Manufacturer:

Maxim Integrated

Description:

Interface - I/O Expanders 16-Bit I/O Port Expander

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MAX7311AAG+

MAX7311AAG+

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