MAX7311AAG+ Datasheet MAX7311ATG+T, MAX7311AUG+, MAX7311ATG+ | P7-P9

Each transmission consists of a START condition sent by

a master, followed by the MAX7311 7-bit slave address

plus R/W bit, a register address byte, 1 or more data

bytes, and finally a STOP condition (Figure 3).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 4).

Acknowledge

The acknowledge bit is a clocked 9th bit, which the

recipient uses as a handshake receipt of each byte of

data (Figure 5). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse, such that the SDA line is sta-

ble low during the high period of the clock pulse. When

the master is transmitting to the MAX7311, the

MAX7311

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

_______________________________________________________________________________________ 7

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 3. START and STOP Conditions

SDA

SCL

DATA LINE STABLE; DATA VALID

CHANGE OF DATA ALLOWED

Figure 4. Bit Transfer

SCL

SDA

BY TRANSMITTER

CLOCK PULSE FOR ACKNOWLEDGMENT

START CONDITION

SDA

BY RECEIVER

12 89

Figure 5. Acknowledge

MAX7311

MAX7311 generates the acknowledge bit since the

MAX7311 is the recipient. When the MAX7311 is trans-

mitting to the master, the master generates the

acknowledge bit.

Slave Address

The MAX7311 has a 7-bit-long slave address (Figure 6).

The 8th bit following the 7-bit slave address is the R/W

bit. Set this bit low for a write command and high for a

read command.

Slave address pins AD2, AD1, and AD0 choose 1 of 64

slave ID addresses (Table 7).

Data Bus Transaction

The command byte is the first byte to follow the 8-bit

device slave address during a write transmission

(Table 1, Figure 7). The command byte is used to deter-

mine which of the following registers are written or read.

Writing to Port Registers

Transmit data to the MAX7311 by sending the device

slave address and setting the LSB to a logic zero. The

command byte is sent after the address and deter-

mines which registers receive the data following the

command byte (Figure 7).

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

8 _______________________________________________________________________________________

SDA

A6 A5 A4 A3 A2 A1 A0

MSB LSB

ACKR/W

PROGRAMMABLE

Figure 6. Slave Address

COMMAND BYTE

ADDRESS (HEX)

FUNCTION PROTOCOL

POWER-UP

DEFAULT

0x00 Input port 1 Read byte XXXX XXXX

0x01 Input port 2 Read byte XXXX XXXX

0x02 Output port 1 Read/write byte 1111 1111

0x03 Output port 2 Read/write byte 1111 1111

0x04 Port 1 polarity inversion Read/write byte 0000 0000

0x05 Port 2 polarity inversion Read/write byte 0000 0000

0x06 Port 1 configuration Read/write byte 1111 1111

0x07 Port 2 configuration Read/write byte 1111 1111

0x08 Timeout register Read/write byte 0000 0001

0xFF Factory reserved. (Do not write to this register.) — —

Table 1. Command Byte Register

123456789

SCL

SDA

S A0000001 76543210A76543210A0A

SLAVE ADDRESS

COMMAND BYTE PORT 1 DATA PORT 2 DATA

R/W

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

START

CONDITION

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

WRITE TO PORT

DATA OUT PORT 1

READ FROM PORT 2

Figure 7. Writes to Output Registers Through Write Byte Protocol

Eight of the MAX7311’s nine registers are configured to

operate as four register pairs: input ports, output ports,

polarity inversion ports, and configuration ports. After

sending 1 byte of data to one register, the next byte is

sent to the other register in the pair. For example, if the

first byte of data is sent to output port 2, then the next

byte of data is stored in output port 1. An unlimited

number of data bytes can be sent in one write transmis-

sion. This allows each 8-bit register to be updated inde-

pendently of the other registers.

Reading Port Registers

To read the device data, the bus master must first send

the MAX7311 address with the R/W bit set to zero, fol-

lowed by the command byte, which determines which

must then send the MAX7311 address with the R/W bit

set to 1. Data from the register defined by the com-

mand byte is then sent from the MAX7311 to the master

(Figures 8, 9).

MAX7311

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

_______________________________________________________________________________________ 9

S 0 A A S 1 A A NA P

SLAVE ADDRESS SLAVE ADDRESS MSB DATA LSB MSB DATA LSBCOMMAND BYTE

R/W R/W

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

MASTER TRANSMITTER BECOMES

MASTER RECEIVER AND SLAVE

RECEIVER BECOMES SLAVE TRANSMITTER

DATA FROM LOWER OR

UPPER BYTE OF REGISTER

DATA FROM LOWER OR

UPPER BYTE OF REGISTER

TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.

Figure 8. Read from Register

123456789

SCL

SLAVE ADDRESS PORT 1 DATA PORT 2 DATA PORT 1 DATA PORT 2 DATAS1777700001PA A A A

R/W

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NONACKNOWLEDGE

FROM MASTER

READ FROM PORT 1

READ FROM PORT 2

DATA INTO PORT 1

DATA INTO PORT 2

INT

TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE

STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS

VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.

Figure 9. Read from Input Registers

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX7311AAG+

Mfr. #:

Buy MAX7311AAG+

Manufacturer:

Maxim Integrated

Description:

Interface - I/O Expanders 16-Bit I/O Port Expander

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX7311AAG+

MAX7311AAG+

Products related to this Datasheet