10
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (OEA/OEB)
When Output Enable (OEA/OEB) is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is disabled (HIGH),
the Q output data bus is in a high-impedance state.
LOAD (LDA/LDB)
The IDT72V805/72V815/72V825/72V835/72V845 devices contain two
12-bit offset registers with data on the inputs, or read on the outputs. When
the Load (LDA/LDB) pin is set LOW and WEN is set LOW, data on the
inputs D0-D11 is written into the Empty offset register on the first LOW-to-
HIGH transition of the Write Clock (WCLK). When the LD pin and WEN are
held LOW then data is written into the Full offset register on the second
LOW-to-HIGH transition of WCLK. The third transition of WCLK again
writes to the Empty offset register.
However, writing all offset registers does not have to occur at one time.
One or two offset registers can be written and then by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When the LD
pin is set LOW, and WEN is LOW, the next offset register in sequence is
written.
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when
the LD pin is set LOW and REN is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read Clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The
read and write pointers operate independently). Offset register content
can be read out in the IDT Standard mode only. It is inhibited in the FWFT
mode.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FLA/FLB)
For the single device mode, see Table I for additional information. In
the Daisy Chain Depth Expansion configuration, FLA/FLB is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXIA/WXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. WXIA/WXIB is connected to Write Expansion Out
(WXOA/WXOB) of the previous device in the Daisy Chain Depth Expan-
sion mode.
READ EXPANSION INPUT (RXIA/RXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. RXIA/RXIB is connected to Read Expansion Out
(RXOA/RXOB) of the previous device in the Daisy Chain Depth Expansion
mode.
OUTPUTS:
FULL FLAG/INPUT READY (FFA/IRA, FFB/IRB)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FFA/
FFB) function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no reads
are performed after a reset, FF will go LOW after D writes to the FIFO.
D = 256 writes for the IDT72V805, 512 for the IDT72V815, 1,024 for the
IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845.
In FWFT mode, the Input Ready (IRA/IRB) function is selected. IR goes
LOW when memory space is available for writing in data. When there is
no longer any free space left, IR goes HIGH, inhibiting further write
operations.
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72V205LB, 513 for the IDT72V215LB, 1,025 for the IDT72V225LB,
2,049 for the IDT72V235LB and 4,097 for the IDT72V245LB. Note that the
additional word in FWFT mode is due to the capacity of the memory plus
output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (EFA/ORA, EFB/ORB)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not
empty.
In FWFT mode, the Output Ready (ORA/ORB) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAFA/PAFB)
The Programmable Almost-Full flag (PAFA/PAFB) will go LOW when
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (RS), the PAF will go LOW after (256-m) writes
for the IDT72V805, (512-m) writes for the IDT72V815, (1,024-m) writes for
the IDT72V825, (2,048–m) writes for the IDT72V835 and (4,096-m) writes
for the IDT72V845. The offset “m” is defined in the FULL offset register.
In FWFT mode, if no reads are performed, PAF will go LOW after (257-
m) writes for the IDT72V805, (513-m) writes for the IDT72V815, (1,025-m)
writes for the IDT72V825, (2,049-m) writes for the IDT72V835 and (4,097-
m) writes for the IDT72V845. The default values for m are noted in Table
1 and 2.
If asynchronous PAF configuration is selected, the PAF is asserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK).
If synchronous PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA/PAEB)
The PAE flag will go LOW when the FIFO reads the almost-empty
condition. In IDT Standard mode, PAE will go LOW when there are n words
or less in the FIFO. In FWFT mode, the PAE will go LOW when there are
n+1 words or less in the FIFO. The offset “n” is defined as the Empty offset.
The default values for n are noted in Table 1 and 2.
If asynchronous PAE configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
