IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
25
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
4295 drw 31
n
n n
RXI
72V805
72V815
72V825
72V835
72V845
WXI
FL
VCC
GND
(0,1)
72V805
72V815
72V825
72V835
72V845
RXI
WXI
FL
VCC
GND
(0,1)
PAF
HF
PAE
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory
with Programmable Flags Used in Depth Expansion Configuration
For an empty expansion configuration, the amount of time it takes for OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the OR flag.
The “ripple down” delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will “bubble up” from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
