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KAI-1003-AAA-CR-B2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
KAI−1003
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10
OPERATION
Table 8. ABSOLUTE MAXIMUM RATINGS
Item Description Min. Max Unit
Temperature
Operation to Specification 0 40 °C
Operation without Damage −10 70 °C
Storage −55 80 °C
Relative Humidity Operation without Damage (Note 1) 0 95 %
Voltage (Between Pins)
SUB − GND (Notes 2, 5) −0.6 50 V
V
RD
, V
SS
, V
DD
− GND −0.6 25 V
V
MIN
− GND −15 0.6 V
All Clocks − GND − 17 V
fV1 − fV2 (Note 3)
− 17 V
fH1 − fH2
− 17 V
fH1, fH2 − fV2
− 17 V
fH2 − OG
− 17 V
V
LG
, OG – GND − 17 V
fR, fH1, fH2 − V
MIN
− 17 V
Capacitance Output Load Capacitance (C
LOAD
) (Note 4) − 10 pF
Current Output Bias Current (I
DD
) (Note 4) − 10 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Without condensation.
2. Under normal operating conditions, the substrate voltage should be maintained above 8.0 V. The substrate voltage should not remain above
25 V for longer than 100 ms.
3. Maximum of 20 V for fV1H − fV2L, with 20 ms maximum duration.
4. Each output.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Table 9. DC OPERATING CONDITIONS
Description Symbol Min. Nom. Max. Unit
Output Gate OG 1.8 2.0 2.2 V
Reset Drain V
RD
10.0 10.5 11.0 V
Output Amplifier Return (Note 1) V
SS
− 0.0 − V
Output Amplifier Load Gate V
LG
1.4 1.5 1.6 V
Output Amplifier Supply V
DD
14.5 15.0 15.5 V
Disable ESD Protection (Note 2) V
MIN
− −8.5 − V
Substrate (Notes 3, 4, 5) V
SUB
8.0 TBS 18.0 V
Ground, P-Well (Note 4) GND − 0.0 − V
1. Current sink.
2. Connect a 0.001 mF capacitor between V
MIN
and GND. V
MIN
must be more negative than the low voltage of any of the fH clocks and should
be established before the fH voltage is applied.
3. DC value when electronic shutter is not in use. See AC Clock Level Conditions for electronic shutter pulse voltage. The operating value of
the substrate voltage, V
SUB
, will be supplied with each shipment.
4. Ground and substrate biases should be established before other gate and diode potentials are applied.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
KAI−1003
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11
Table 10. AC CLOCK LEVEL CONDITIONS
Description Level Symbol Min. Nom. Max. Unit
Vertical CCD Clocks
(Note 1)
High
fV2H
9.5 10.5 11.5 V
Mid
fV1M, fV2M
−0.8 −0.5 0.0 V
Low
fV1L, fV2L
−9.0 −8.5 −8.0 V
Horizontal CCD Clocks
(Note 1)
High
fH1H, fH2H
4.5 5.0 5.5 V
Low
fH1L, fH2L
−6.5 −6.0 −5.5 V
Reset Clock
Amplitude
fR
SWING
− 5.0 − V
Low (Note 2)
V
f
Rlow
0 TBS 5.0 V
Electronic Shutter Pulse (Notes 3, 4) Shutter V
SHUTTER
37 40 45 V
1. For best results, the CCD clock swings must be greater than or equal to the nominal values.
2. Reset clock low level voltage will be supplied with each shipment.
3. Electronic shutter pulse voltage referenced to GND. See DC Operating Conditions for DC level when electronic shutter is not in use.
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Electronic Shutter Operation
Electronic shuttering is accomplished by pulsing the
substrate voltage to empty the photodiodes. See Figure 16
for timing. The pulse must not occur while useful
information is being read from a line.
Table 11. CALCULATED CLOCK CAPACITANCE
Description Phase Symbol Typical Unit
Vertical CCD Clocks
(Note 1)
1 to GND
C fV1
55/37 nF
2 to GND
C fV2
50/32 nF
1 to 2
C fV1 − fV2
4 nF
Horizontal CCD Clocks
(Notes 1, 2)
1A
C fH1A
58/21 pF
1B
C fH1B
41/13 pF
1C
C fH1C
15/10 pF
2A
C fH2A
48/22 pF
2B
C fH2B
30/11 pF
2C
C fH2C
18/13 pF
HCCD Summing Clock
C fH22A/B
3 pF
Reset Clock − GND
C fRA/B
5 pF
1. Accumulation/depletion capacitances.
2. Capacitance of this gate to GND and all other gates.
KAI−1003
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12
Table 12. AC TIMING REQUIREMENTS
Description Symbol Min. Nom. Max. Unit
Vertical High Level Duration t
V2H
15 − 20
ms
Vertical Transfer Time (Note 1) t
V
1.0 2.0/1.0 −
ms
Vertical Pedestal Delay 1 & 3 t
VPD1
, t
VPD3
40 − −
ms
Vertical Pedestal Delay 2 t
VPD2
15 − −
ms
Horizontal Delay (Note 1) t
HD
1.5/0.5 − −
ms
Reset Duration (Note 2) t
R
− 10 − ns
Horizontal CCD Clock Frequency (Note 3) f
H
− 20 − MHz
Pixel Time t
H
− 50 − ns
Line Time (Note 4) t
L
− − −
Frame Time (Note 4) t
F
− − −
Clamp Delay (Note 5) t
CD
− − − ns
Sample Delay (Note 5) t
SD
− − − ns
Electronic Shutter Pulse Duration t
ES
5 7.5 10
ms
Electronic Shutter Horizontal Delay t
ESHD
1.0 − −
ms
1. Non-binning/binning times.
2. The rising edge of fR should be coincident with the rising edge of fH22, within ±5 ns.
3. Horizontal CCD clock frequency can be increased to 40 MHz, with increased readout noise.
4. See Table 4 for nominal line and frame time in each mode.
5. The clamp delay and sample delay should be adjusted for optimum results.
Table 13. CCD CLOCK WAVEFORM CONDITIONS
Description Phase Symbol t
WH
t
WL
t
R
t
F
Unit
NON-BINNING
Vertical CCD Clocks
1
fV1M/L
− 1.5 0.5 0.5
ms
2
fV2M/L
1.5 − 0.5 0.5
ms
2, High
fV2H
15 1.0 1.0
ms
Horizontal CCD Clocks
1
fH1
20.5 21.5 4.0 4.0 ns
2
fH2
20.5 21.5 4.0 4.0 ns
2, Binning (Note 1)
fH22
20.5 21.5 4.0 4.0 ns
Reset clock
fR
5 39 3 3 ns
2y2 BINNING
Vertical CCD Clocks
1 (Note 2)
fV1M/L
0.5 0.5 0.5 0.5
ms
2 (Note 2)
fV2M/L
0.5 0.5 0.5 0.5
ms
2, High
fV2H
15 − 1.0 1.0
ms
Horizontal CCD Clocks
1
fH1
20.5 21.5 4.0 4.0 ns
2
fH2
20.5 21.5 4.0 4.0 ns
2, Binning
fH22
46.0 46.0 4.0 4.0 ns
Reset clock
fR
5 89 3 3 ns
1. Typical values measured with clocks connected to image sensor device. The actual values should be optimized for particular board layout.
2. fH22 may be connected to fH2 in 1×1 mode.
3. t
WH
and t
WL
for fV1M/L and fV2M/L are the time periods during the double pulses.
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KAI-1003-AAA-CR-B2

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Manufacturer:
ON Semiconductor
Description:
Image Sensors INTERLINE CCD IMAGE SENSOR
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