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E-TDA7333013TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
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Functional description TDA7333
16/26
3.7.1 rds_int register
Figure 9. rds_int register
3.7.2 rds_qu register
Figure 10. rds_qu register
Note : when changing the interrupt mode, one has to
perform a reset of the module (i.e set the bit “ar_res” at
one)
interrupt bit. It is set to one on every programmed interrupt. It
is reset by reading rds_int register.
interrupt source
itsrc[2:0] select the interrupt source
(1)
synchronization information.
1: the module is already synchronized.
0: the module is synchronizing
It is used to force a resynchronization. If it is set to one, the
RDS modules are forced to resynchronization state.
The bit is automatically reset. So it is always read as zero.
RDS block.
if 1, one block has been detected
rds_int and rds_bd_ctrl write order (
when in SPI mode
)
1: rds_int and rds_bd_ctrl are updated with data shifted in.
0: rds_int and rds_bd_ctrl are not updated.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
r/w r r/w r r/w r/w r/w r
write bne ar_res synch itsrc2 itsrc1 itsrc0 int
00000
00
0
(1)
00
interrupt source i tsrc2 itsrc1 itsrc0
no interrupt
RDS Block
block A
block B
block D
TA
TAEON
0
010
011
110
111
101
rds_int
reset value
bit name
access
001
(3) qu[3..0] is a counter of the quality bit information coming
from the RDS demodulator. It is counting the number of bits
which are marked as bad by the demodulator. Only those bits
are allowed to be corrected. Thus the quality bit counter indi-
cates the maximum possible number of bits being corrected.
It indicates if the error correction was successfull.
1: the syndrome was zero after the error correction.
0: the syndrome did not become zero and therefore the
correction was not successfull.
1: a block E is detected.This indicates a paging block
which is defined in the RBDS specification used in the
united states of America.
0: an ordinary RDS block A, B, C, c·or D is detected, or no
valid syndrome was found.
bit 0 of block counter (2)
bit 1 of block counter (2)
bit 0 of quality counter
(3)
bit 1 of quality counter
(3)
bit 2 of quality counter
(3)
bit 3 of quality counter
(3)
bit name
access
bit 7 bit 0bit 1bit 2bit 3bit 4bit 5bit 6
r
r
rr
rrr
r
synzequ0qu3 qu1qu2 blk1 blk0
blk1
10
00
blk0
block A
block name
block D
1block C,C’ 0
block B
11
(2)
reset value
0
0
00
000
0
rds_qu
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TDA7333 Functional description
17/26
3.7.3 rds_corrp register
Figure 11. rds_corrp register
3.7.4 rds_bd_h register
Figure 12. rds_bd_h register
(*) (refer to: Specification of the radio data system EN50067
of CENELEC, ANNEX B). When bits 4...0 of the syndrome
register are all zero a possible error burst is stored in this
bits. With the help of the correction pattern(bits 9..5 of the
syndrome register), the type of error can be measured in or-
der to classify the reliability of the correction.
It is an information about a correct syndrome after recep-
tion resp. after an error correction routine.
1: a correct syndrome was detected.
0: the syndrome was wrong. The current RDS data cannot
be used.
It is an information about error correction.
1: an error correction was made.
0: the actual RDS block is detected as error free.
bit 5 of the syndrome register(*)
bit 6 of the syndrome register(*)
bit 7 of the syndrome register(*)
bit 8 of the syndrome register(*)
bit 9 of the syndrome register(*)
access r r r r r r r r
-
correct data_ok
rds_comp bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
reset value 0 0 0 0 0 0 0 0
bit name cp9 cp8 cp7 cp6 cp5
bit 15 of the actual RDS 16bits information
bit 14 of the actual RDS 16bits information
bit 13 of the actual RDS 16bits information
bit 12 of the actual RDS 16bits information
bit 11 of the actual RDS 16bits information
bit 10 of the actual RDS 16bits information
bit 9 of the actual RDS 16bits information
bit 8 of the actual RDS 16bits information
bit name
access
bit 7 bit 0bit 1bit 2bit 3bit 4bit 5bit 6
r
r
rr
rrr
r
m8m9m12m15 m13m14 m11 m10
reset value
0
0
00
000
0
rd s_ b d _h
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Functional description TDA7333
18/26
3.7.5 rds_bd_l register
Figure 13. rds_bd_l register
3.7.6 rds_bd_ctrl register
Figure 14. rds_bd_ctrl register
Note: Sinc4reg and testreg are reserved registers dedicated to testing and evaluation.
bit 7 of the actual RDS 16bits information
bit 6 of the actual RDS 16bits information
bit 5 of the actual RDS 16bits information
bit 4 of the actual RDS 16bits information
bit 3 of the actual RDS 16bits information
bit 2 of the actual RDS 16bits information
bit 1of the actual RDS 16bits information
bit 0 of the actual RDS 16bits information
access
bit 7 bit 0bit 1bit 2bit 3bit 4bit 5bit 6
r
r
rr
rrr
r
m0m1m4m7 m5m6 m3 m2
reset value
bit name
0
0
00
000
0
rds_bd_I
(3)
select sensitivity of quality bit.
00: minimum (reset value)
11: maximum
select PLL’s time constants by software or hardware:
1: software. Time constants are selected by pllb[1:0] resp.
pllf
0: hardware. (reset value) Time constants automatically
increase after a reset.
set the 57kHz pll time constant
(1)
bit 0 of 1187.5Hz pll time constant
(2)
bit 1 of 1187.5Hz pll time constant
(2)
bit 0 of quality sensitivity
(3)
bit 1 of quality sensitivity
(3)
select oscillator frequency:
1: 8.664MHz
0: 8.55MHz (reset value)
bit name
access
r
r/w r/w r/w r/w r/w r/w r/w
shw -pllb1
pllb1 pllb0
pllb0freq qsens1qsens0 pllf
pllf
lock time needed for 90 deg deviation
10
00
10
11
(2)
reset value
1
0
00
00 0
0
(1)
0
1
2 ms
10 ms
lock time needed for 90 deg deviation
5 ms (reset status)
15 ms
35 ms
76 ms
rds_bd_ctrl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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E-TDA7333013TR

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Manufacturer:
STMicroelectronics
Description:
IC DEMODULATOR 16TSSOP
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