CY7C1011DV33
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05609 Rev. *H Revised November 12, 2014
2-Mbit (128 K × 16) Static RAM
Features
■ Pin-and function-compatible with CY7C1011CV33
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 90 mA @ 10 ns (Industrial)
■ Low CMOS standby power
❐ I
SB2
= 10 mA
■ Data Retention at 2.0 V
■ Automatic power-down when deselected
■ Independent control of upper and lower bits
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
Functional Description
The CY7C1011DV33
[1]
is a high-performance CMOS Static
RAM organized as 128 K words by 16 bits.
Writing to the device is accomplished by taking Chip Enable (CE
)
and Write Enable (WE
) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into
the location specified on the address pins (A
0
through A
16
). If
Byte High Enable (BHE
) is LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15
. See the truth table
at the back of this data sheet for a complete description of read
and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), the BHE and BLE are
disabled (BHE
, BLE HIGH), or during a write operation (CE LOW,
and WE
LOW).
The CY7C1011DV33 is available in standard Pb-free 44-pin
TSOP II with center power and ground pinout, as well as 48-ball
very fine-pitch ball grid array (VFBGA) packages.
For a complete list of related resources, click here.
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
128K X 16
A
0
A
11
A
13
A
12
A
A
A
16
A
9
A
10
I/O
0
–I/O
7
OE
I/O
8
–I/O
15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com
