Document Number: 38-05609 Rev. *H Page 7 of 17
AC Switching Characteristics
Over the Operating Range
Parameter
[9]
Description
-10
Unit
Min Max
Read Cycle
t
power
[10]
V
CC
(typical) to the first access 100 – s
t
RC
Read cycle time 10 – ns
t
AA
Address to data valid – 10 ns
t
OHA
Data hold from address change 3 – ns
t
ACE
CE LOW to data valid – 10 ns
t
DOE
OE LOW to data valid – 5 ns
t
LZOE
OE LOW to low Z
[11]
0–ns
t
HZOE
OE HIGH to high Z
[11, 12]
–5ns
t
LZCE
CE LOW to low Z
[11]
3–ns
t
HZCE
CE HIGH to high Z
[11, 12]
–5ns
t
PU
CE LOW to power-up 0 – ns
t
PD
CE HIGH to power-down – 10 ns
t
DBE
Byte enable to data valid – 5 ns
t
LZBE
Byte enable to low Z 0 – ns
t
HZBE
Byte disable to high Z – 6 ns
Write Cycle
[13, 14]
t
WC
Write cycle time 10 – ns
t
SCE
CE LOW to write end 7 – ns
t
AW
Address set-up to write end 7 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address set-up to write start 0 – ns
t
PWE
WE pulse width 7–ns
t
SD
Data set-up to write end 5 – ns
t
HD
Data hold from write end 0 – ns
t
LZWE
WE HIGH to low Z
[11]
3–ns
t
HZWE
WE LOW to high Z
[11, 12]
–5ns
t
BW
Byte enable to end of write 7 – ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
10. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access is performed.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZBE
is less than t
LZBE
,
and t
HZWE
is less than t
LZWE
for any given
device.
12. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high
impedance state.
13. The internal write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
14. The minimum write cycle pulse width for Write Cycle No. 4 (WE
Controlled, OE LOW) should be the sum of t
SD
and t
HZWE
.
