APRIL 2006
DSC-6450/0A
1
©2006 Integrated Device Technology, Inc.
Features
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128K x 36, 256K x 18 memory configurations
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Supports fast access times:
Commercial:
– 6.5ns up to 133MHz clock frequency
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
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LBO input selects interleaved or linear burst mode
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Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
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3.3V core power supply
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Power down controlled by ZZ input
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3.3V I/O
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Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
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Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V3579.
Description
The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
A
0
-A
17
Address Inputs Input Synchronous
CE
Chip Enable Input Synchronous
CS
0
, CS
1
Chip Selects Input Synchronous
OE
Output Enable Input Asynchronous
GW
Global Write Enable Input Synchronous
BWE
Byte Write Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV
Burst Address Advance Input Synchronous
ADSC
Address Status (Cache Controller) Input Synchronous
ADSP
Address Status (Processor) Input Synchronous
LBO
Linear / Interleaved Burst Order Input DC
TMS Test Mode Select Input Synchronous
TDI Test Data Input Input Synchronous
TCK Test Clock Input N/A
TDO Test Data Output Output Synchronous
TRST
JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output I/O Synchronous
V
DD
, V
DDQ
Core Power, I/O Power Supply N/A
V
SS
Ground Supply N/A
6450tbl 01
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V3577YS
IDT71V3579YS
IDT71V3577YSA
IDT71V3579YSA
