NCP1230
www.onsemi.com
12
Feedback
The feedback pin has been designed to be connected
directly to the open−collector output of an optocoupler. The
pin is pulled−up through a 20 k resistor to the internal
Vdd_fb supply (5 volts nominal). The feedback input signal
is divided down, by a factor of three, and connected to the
negative (−) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 30).
The NCP1230 is a peak current mode controller, where
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turns−on and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
Flip−Flop, turning off the power switch until the next
oscillator clock cycle begins.
Figure 30.
Vdd_fb
+
−
FB
PWM
2.3 Vpp
Ramp
LEB
20k
18k
25k
55k
10 V
2
3
The feedback pin input is clamped to a nominal 10 volt for
ESD protection.
Skip Mode
The feedback input is connected in parallel with the skip
cycle logic (Figure 31). When the feedback voltage drops
below 25% of the maximum peak current (1.0 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
V
c
+ I
pk
@ R
s
@ 3
where:
V
c
= control voltage (Feedback pin input),
I
pk
= Peak primary current,
R
s
= Current sense resistor,
3 = Feedback divider ratio.
SkipLevel + 3V @ 25% + 0.75V
I
pk
+
0.75
R
s
@ 3
where:
I
pk
@ R
s
+ 1V
I
pk
+
2 @ P
in
L
p
@ f
Ǹ
where:
P
in
= is the power level where the NCP1230 will go into
the skip mode
L
p
= Primary inductance
f = NCP1230 controller frequency
P
in
+
L
p
@ f @ I
pk
2
2
P
in
+
P
out
Eff
where:
Eff = the power supply efficiency
R
out
+
E
out
2
P
out
Figure 31.
+
125 ms
−
+
−
+
FB
+
Vskip
S
R
PFC_V
CC
CS Cmp
Latch
Reset
Vskip
/ Vstby−out
S is rising edge triggered
R is falling edge triggered
Vdd_fb
1.25 V
0.75 V
During the skip mode the PFC_Vcc signal (pin 1) is
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 32 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 125 msec timer starts, and if the
conditions is still present after the time output period, the
