NCP1230
www.onsemi.com
14
Leading Edge Blanking
In Switch Mode Power Supplies (SMPS) there can be a
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 34) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
Figure 34.
-
+
+
-
CS
Vccreset
Latch−Off
R
S
Q
FB/3
2.3 Vpp
Ramp
Thermal Shutdown
Skip
125 msec Timer
PWM Comparator
18 k
10 V
LEB
3 V
3
250 ns
Short−Circuit Condition
The NCP1230 is different from other controllers which
use an auxiliary windings to detect events on the isolated
secondary output. There maybe some conditions (for
example when the leakage inductance is high) where it can
be extremely difficult to implement short−circuit and
overload protection. This occurs because when the power
switch opens, the leakage inductance superimposes a large
spike on the switch drain voltage. This spike is seen on the
isolated secondary output and on the auxiliary winding.
Because the auxiliary winding and diode form a peak
rectifier, the auxiliary Vcc capacitor voltage can be charged
up to the peak value rather than the true plateau which is
proportional to the output level.
To resolve these issues the NCP1230 monitors the 1.0 V
error flag. As soon as the internal 1.0 V error flag is asserted
high, a 125 ms timer starts. If at the end of the 125 ms timeout
period, the error flag is still asserted then the controller
determines that there is a true fault condition and stops the
PWM drive output, refer to Figure 35. When this occurs,
Vcc starts to decrease because the power supply is locked
out. When Vcc drops below UVLOlow (7.7 V typical), it
enters a latch−off phase where the internal consumption is
reduced down to 680 A (typical). The voltage on the Vcc
capacitor continues to drop, but at a lower rate. When Vcc
reaches the latch−off level (5.6 V), the current source is
turned on and pulls Vcc above UVLOhigh. To limit the fault
output power, a divide−by−two circuit is connected to the
Vcc pin that requires two startup sequences before
attempting to restart the power supply. If the fault has gone
and the error flag is low, the controller resumes normal
operations.
Under transient load conditions, if the error flag is
asserted, the error flag will normally drop prior to the 125 ms
timeout period and the controller continues to operate
normally.
If the 125 msec timer expires while the NCP1230 is in the
Skip Mode, SW1 opens and the PFC_Vcc output will shut
down and will not be activated until the fault goes away and
the power supply resumes normal operations.
While in the Skip Mode, to avoid any thermal runaway it
is desirable for the Burst duty cycle to be kept below
20%(the burst duty−cycle is defined as Tpulse / Tfault).
