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74LVCH8T245BQ,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 9 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] V
CCI
is the supply voltage associated with the data input port.
[2] V
CCO
is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least I
BHLO
/ I
BHHO
when the input is in the range V
IL
to V
IH
.
[4] For non bus hold parts only (74LVC8T245).
I
CC
supply current A port; V
I
= 0 V or V
CCI
; I
O
= 0 A
[1]
V
CC(A)
, V
CC(B)
= 1.2 V to 5.5 V - 15 - 20 A
V
CC(A)
= 5.5 V; V
CC(B)
= 0 V - 15 - 20 A
V
CC(A)
= 0 V; V
CC(B)
= 5.5 V 2-4-A
B port; V
I
= 0 V or V
CCI
; I
O
= 0 A
V
CC(A)
, V
CC(B)
= 1.2 V to 5.5 V - 15 - 20 A
V
CC(B)
= 0 V; V
CC(A)
= 5.5 V 2-4-A
V
CC(B)
= 5.5 V; V
CC(A)
= 0 V - 15 - 20 A
A plus B port (I
CC(A)
+ I
CC(B)
);
I
O
=0A; V
I
=0 Vor V
CCI
V
CC(A)
, V
CC(B)
= 1.2 V to 5.5 V - 25 - 30 A
I
CC
additional
supply current
per input;
V
CC(A)
,V
CC(B)
= 3.0 V to 5.5 V
DIR and OE
input; DIR or OE
input at V
CC(A)
0.6 V;
AportatV
CC(A)
or GND;
B port = open
-50-75A
A port; A port at V
CC(A)
0.6 V;
DIR at V
CC(A)
; B port = open
[4]
-50-75A
B port; B port at V
CC(B)
0.6 V;
DIR at GND; A port = open
[4]
-50-75A
Table 7. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 10 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[2] f
i
= 10 MHz; V
I
=GNDtoV
CC
; t
r
= t
f
= 1 ns; C
L
= 0 pF; R
L
= .
Table 8. Typical dynamic characteristics at V
CC(A)
= 1.2 V and T
amb
= 25 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Symbol Parameter Conditions V
CC(B)
Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
t
pd
propagation delay An to Bn 11.0 8.5 7.4 6.2 5.7 5.4 ns
Bn to An 11.0 10.0 9.5 9.1 8.9 8.9 ns
t
dis
disable time OE to An 9.5 9.5 9.5 9.5 9.5 9.5 ns
OE
to Bn 10.2 8.2 7.8 6.7 7.3 6.4 ns
t
en
enable time OE to An 13.5 13.5 13.5 13.5 13.5 13.5 ns
OE
to Bn 13.6 10.3 8.9 7.5 7.1 7.0 ns
Table 9. Typical dynamic characteristics at V
CC(B)
= 1.2 V and T
amb
= 25 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Symbol Parameter Conditions V
CC(A)
Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
t
pd
propagation delay An to Bn 11.0 10.0 9.5 9.1 8.9 8.8 ns
Bn to An 11.0 8.5 7.3 6.2 5.7 5.4 ns
t
dis
disable time OE to An 9.5 6.8 5.4 3.8 4.1 3.1 ns
OE
to Bn 10.2 9.1 8.6 8.1 7.8 7.8 ns
t
en
enable time OE to An 13.5 9.0 6.9 4.8 3.8 3.2 ns
OE
to Bn 13.6 12.5 12.0 11.5 11.4 11.4 ns
Table 10. Typical power dissipation capacitance at V
CC(A)
= V
CC(B)
and T
amb
= 25 C
[1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions V
CC(A)
and V
CC(B)
Unit
1.8 V 2.5 V 3.3 V 5.0 V
C
PD
power dissipation
capacitance
A port: (direction A to B);
B port: (direction B to A)
1112pF
A port: (direction B to A);
B port: (direction A to B)
13 13 13 13 pF
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 11 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
Table 11. Dynamic characteristics for temperature range 40 C to +85 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
V
CC(A)
= 1.5 V 0.1 V
t
pd
propagation
delay
An to Bn 1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 ns
Bn to An 0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns
t
dis
disable time OE to An 1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 ns
OE
to Bn 2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns
t
en
enable time OE to An 0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 ns
OE
to Bn 1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns
V
CC(A)
= 1.8 V 0.15 V
t
pd
propagation
delay
An to Bn 1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 ns
Bn to An 0.9 23 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns
t
dis
disable time OE to An 1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns
OE
to Bn 2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns
t
en
enable time OE to An 0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 ns
OE
to Bn 1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns
V
CC(A)
= 2.5 V 0.2 V
t
pd
propagation
delay
An to Bn 1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 ns
Bn to An 1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns
t
dis
disable time OE to An 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 ns
OE
to Bn 2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns
t
en
enable time OE to An 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 ns
OE
to Bn 1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns
V
CC(A)
= 3.3 V 0.3 V
t
pd
propagation
delay
An to Bn 1.5 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns
Bn to An 0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns
t
dis
disable time OE to An 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns
OE
to Bn 2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns
t
en
enable time OE to An 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns
OE
to Bn 1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns
V
CC(A)
= 5.0 V 0.5 V
t
pd
propagation
delay
An to Bn 1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 ns
Bn to An 0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns
t
dis
disable time OE to An 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns
OE
to Bn 2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns
t
en
enable time OE to An 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns
OE
to Bn 1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

74LVCH8T245BQ,118

Mfr. #:
Buy 74LVCH8T245BQ,118
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 8-BIT DUAL SUPPLY TRANSLATING XCVR 3-S
Lifecycle:
New from this manufacturer.
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